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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides a behavioral model of generic    ////
////  single-port synchronous RAM.                                ////
////  It also contains a synthesizeable model for FPGAs.          ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Generic FPGA (VENDOR_FPGA)                                ////
////    Tested RAMs: Altera, Xilinx                               ////
////    Synthesis tools: LeonardoSpectrum, Synplicity             ////
////  - Xilinx (VENDOR_XILINX)                                    ////
////  - Altera (VENDOR_ALTERA)                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Richard Herveille, richard@asics.ws                   ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/11/08 19:32:59  samg
// corrected output: output not valid if ce low
//
// Revision 1.1.1.1  2001/09/14 09:57:09  rherveille
// Major cleanup.
// Files are now compliant to Altera & Xilinx memories.
// Memories are now compatible, i.e. drop-in replacements.
// Added synthesizeable generic FPGA description.
// Created "generic_memories" cvs entry.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
//`include "timescale.v"
 
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
//`define VENDOR_FPGA
 
module generic_spram(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
        //
        // Default address and data buses width
        //
        parameter aw = 6; //number of address-bits
        parameter dw = 8; //number of data-bits
 
        //
        // Generic synchronous single-port RAM interface
        //
        input           clk;  // Clock, rising edge
        input           rst;  // Reset, active high
        input           ce;   // Chip enable input, active high
        input           we;   // Write enable input, active high
        input           oe;   // Output enable input, active high
        input  [aw-1:0] addr; // address bus inputs
        input  [dw-1:0] di;   // input data bus
        output [dw-1:0] do;   // output data bus
 
        //
        // Module body
        //
 
`ifdef VENDOR_FPGA
        //
        // Instantiation synthesizeable FPGA memory
        //
        // This code has been tested using LeonardoSpectrum and Synplicity.
        // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
        //
        reg [dw-1 :0] mem [(1<<aw) -1:0];
        reg [aw-1:0] raddr;
 
        always@(posedge clk)
        begin
                // read operation
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
                // write operation
                if (we && ce)
                        mem[addr] <= #1 di;
        end
 
        assign #1 do = mem[raddr];
 
`else
 
`ifdef VENDOR_XILINX
 
        wire [dw-1:0] q;  // output from xilinx ram
        //
        // Instantiation of FPGA memory:
        //
        // Virtex/Spartan2 BlockRAMs
        //
        xilinx_ram_sp xilinx_ram(
                .clk(clk),
                .rst(rst),
                .addr(addr),
                .di(di),
                .en(ce),
                .we(we),
                .do(do)
        );
 
        defparam
                xilinx_ram.dwidth = dw,
                xilinx_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ALTERA
 
        //
        // Instantiation of FPGA memory:
        //
        // Altera FLEX EABs
        //
 
        altera_ram_sp altera_ram(
                .inclock(clk),
                .address(addr),
                .data(di),
                .we(we && ce),
                .q(do)
        );
 
        defparam
                altera_ram.dwidth = dw,
                altera_ram.awidth = aw;
 
`else
 
`ifdef VENDOR_ARTISAN
 
        //
        // Instantiation of ASIC memory:
        //
        // Artisan Synchronous Single-Port RAM (ra1sh)
        //
        artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(
                .CLK(clk),
                .CEN(~ce),
                .WEN(~we),
                .A(addr),
                .D(di),
                .OEN(~oe),
                .Q(do)
        );
 
`else
 
`ifdef VENDOR_AVANT
 
        //
        // Instantiation of ASIC memory:
        //
        // Avant! Asynchronous Two-Port RAM
        //
        avant_atp avant_atp(
                .web(~we),
                .reb(),
                .oeb(~oe),
                .rcsb(),
                .wcsb(),
                .ra(addr),
                .wa(addr),
                .di(di),
                .do(do)
        );
 
`else
 
`ifdef VENDOR_VIRAGE
 
        //
        // Instantiation of ASIC memory:
        //
        // Virage Synchronous 1-port R/W RAM
        //
        virage_ssp virage_ssp(
                .clk(clk),
                .adr(addr),
                .d(di),
                .we(we),
                .oe(oe),
                .me(ce),
                .q(do)
        );
 
`else
 
`ifdef VENDOR_VIRTUALSILICON
 
        //
        // Instantiation of ASIC memory:
        //
        // Virtual Silicon Single-Port Synchronous SRAM
        //
        virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(
                .CK(clk),
                .ADR(addr),
                .DI(di),
                .WEN(~we),
                .CEN(~ce),
                .OEN(~oe),
                .DOUT(do)
        );
 
`else
 
        //
        // Generic single-port synchronous RAM model
        //
 
        //
        // Generic RAM's registers and wires
        //
        reg  [dw-1:0] mem [(1<<aw)-1:0];  // RAM content
        wire [dw-1:0] q;                 // RAM output
        reg  [aw-1:0] raddr;             // RAM read address
        //
        // Data output drivers
        //
        assign do = (oe & ce) ? q : {dw{1'bz}};
 
        //
        // RAM read and write
        //
 
        // read operation
        always@(posedge clk)
        if (ce) // && !we)
                raddr <= #1 addr;    // read address needs to be registered to read clock
 
        assign #1 q = rst ? {dw{1'b0}} : mem[raddr];
 
        // write operation
        always@(posedge clk)
                if (ce && we)
                        mem[addr] <= #1 di;
 
        // Task prints range of memory
        // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
        task print_ram;
        input [aw-1:0] start;
        input [aw-1:0] finish;
        integer rnum;
        begin
                for (rnum=start;rnum<=finish;rnum=rnum+1)
                        $display("Addr %h = %h",rnum,mem[rnum]);
        end
        endtask
 
`endif // !VIRTUALSILICON_SSP
`endif // !VIRAGE_SSP
`endif // !AVANT_ATP
`endif // !ARTISAN_SSP
`endif // !VENDOR_ALTERA
`endif // !VENDOR_XILINX
`endif // !VENDOR_FPGA
 
endmodule
 
 
//
// Black-box modules
//
 
`ifdef VENDOR_ALTERA
        module altera_ram_sp (
                address,
                inclock,
                we,
                data,
                q) /* synthesis black_box */;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input  [awidth -1:0] address;
                input                inclock;
                input                we;
                input  [dwidth -1:0] data;
                output [dwidth -1:0] q;
 
                // synopsis translate_off
                // exemplar translate_off
 
                syn_ram_irou #(
                        "UNUSED",
                        dwidth,
                        awidth,
                        1 << awidth
                )
                altera_spram_model (
                        .Inclock(inclock),
                        .Address(address),
                        .Data(data),
                        .WE(we),
                        .Q(q)
                );
 
                // exemplar translate_on
                // synopsis translate_on
 
        endmodule
`endif // VENDOR_ALTERA
 
`ifdef VENDOR_XILINX
        module xilinx_ram_sp (
                        clk,
                        rst,
                        addr,
                        di,
                        en,
                        we,
                        do) /* synthesis black_box */ ;
 
                parameter awidth = 7;
                parameter dwidth = 8;
 
                input                clk;
                input                rst;
                input  [awidth -1:0] addr;
                input  [dwidth -1:0] di;
                input                en;
                input                we;
                output [dwidth -1:0] do;
 
                // insert simulation model
 
 
                // synopsys translate_off
                // exemplar translate_off
 
                C_MEM_SP_BLOCK_V1_0 #(
                        awidth,
                        1,
                        "0",
                        1 << awidth,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        1,
                        "",
                        16,
                        0,
                        0,
                        1,
                        1,
                        dwidth
                )
                xilinx_spram_model (
                        .CLK(clk),
                        .RST(rst),
                        .ADDR(addr),
                        .DI(di),
                        .EN(en),
                        .WE(we),
                        .DO(do)
                );
 
                // exemplar translate_on
                // synopsys translate_on
 
        endmodule
`endif // VENDOR_XILINX
 

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[/] [sxp/] [trunk/] [ram/] [generic_spram.v] - Blame information for rev 59

Line No.	Rev	Author	Line
1	41	samg	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides a behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It also contains a synthesizeable model for FPGAs. ////`
15			`//// It should be used in all OPENCORES designs that want to be ////`
16			`//// portable accross different target technologies and ////`
17			`//// independent of target memory. ////`
18			`//// ////`
19			`//// Supported ASIC RAMs are: ////`
20			`//// - Artisan Single-Port Sync RAM ////`
21			`//// - Avant! Two-Port Sync RAM (*) ////`
22			`//// - Virage Single-Port Sync RAM ////`
23			`//// - Virtual Silicon Single-Port Sync RAM ////`
24			`//// ////`
25			`//// Supported FPGA RAMs are: ////`
26			`//// - Generic FPGA (VENDOR_FPGA) ////`
27			`//// Tested RAMs: Altera, Xilinx ////`
28			`//// Synthesis tools: LeonardoSpectrum, Synplicity ////`
29			`//// - Xilinx (VENDOR_XILINX) ////`
30			`//// - Altera (VENDOR_ALTERA) ////`
31			`//// ////`
32			`//// To Do: ////`
33			`//// - fix avant! two-port ram ////`
34			`//// - add additional RAMs ////`
35			`//// ////`
36			`//// Author(s): ////`
37			`//// - Richard Herveille, richard@asics.ws ////`
38			`//// - Damjan Lampret, lampret@opencores.org ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//// ////`
42			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
43			`//// ////`
44			`//// This source file may be used and distributed without ////`
45			`//// restriction provided that this copyright statement is not ////`
46			`//// removed from the file and that any derivative work contains ////`
47			`//// the original copyright notice and the associated disclaimer. ////`
48			`//// ////`
49			`//// This source file is free software; you can redistribute it ////`
50			`//// and/or modify it under the terms of the GNU Lesser General ////`
51			`//// Public License as published by the Free Software Foundation; ////`
52			`//// either version 2.1 of the License, or (at your option) any ////`
53			`//// later version. ////`
54			`//// ////`
55			`//// This source is distributed in the hope that it will be ////`
56			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
57			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
58			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
59			`//// details. ////`
60			`//// ////`
61			`//// You should have received a copy of the GNU Lesser General ////`
62			`//// Public License along with this source; if not, download it ////`
63			`//// from http://www.opencores.org/lgpl.shtml ////`
64			`//// ////`
65			`//////////////////////////////////////////////////////////////////////`
66			`//`
67			`// CVS Revision History`
68			`//`
69			`// $Log: not supported by cvs2svn $`
70			`// Revision 1.2 2001/11/08 19:32:59 samg`
71			`// corrected output: output not valid if ce low`
72			`//`
73			`// Revision 1.1.1.1 2001/09/14 09:57:09 rherveille`
74			`// Major cleanup.`
75			`// Files are now compliant to Altera & Xilinx memories.`
76			`// Memories are now compatible, i.e. drop-in replacements.`
77			`// Added synthesizeable generic FPGA description.`
78			`// Created "generic_memories" cvs entry.`
79			`//`
80			`// Revision 1.2 2001/07/30 05:38:02 lampret`
81			`// Adding empty directories required by HDL coding guidelines`
82			`//`
83			`//`
84
85			//`include "timescale.v"
86
87			//`define VENDOR_XILINX
88			//`define VENDOR_ALTERA
89			//`define VENDOR_FPGA
90
91			`module generic_spram(`
92			`// Generic synchronous single-port RAM interface`
93			`clk, rst, ce, we, oe, addr, di, do`
94			`);`
95
96			`//`
97			`// Default address and data buses width`
98			`//`
99			`parameter aw = 6; //number of address-bits`
100			`parameter dw = 8; //number of data-bits`
101
102			`//`
103			`// Generic synchronous single-port RAM interface`
104			`//`
105			`input clk; // Clock, rising edge`
106			`input rst; // Reset, active high`
107			`input ce; // Chip enable input, active high`
108			`input we; // Write enable input, active high`
109			`input oe; // Output enable input, active high`
110			`input [aw-1:0] addr; // address bus inputs`
111			`input [dw-1:0] di; // input data bus`
112			`output [dw-1:0] do; // output data bus`
113
114			`//`
115			`// Module body`
116			`//`
117
118			`ifdef VENDOR_FPGA
119			`//`
120			`// Instantiation synthesizeable FPGA memory`
121			`//`
122			`// This code has been tested using LeonardoSpectrum and Synplicity.`
123			`// The code correctly instantiates Altera EABs and Xilinx BlockRAMs.`
124			`//`
125			`reg [dw-1 :0] mem [(1<<aw) -1:0];`
126			`reg [aw-1:0] raddr;`
127
128			`always@(posedge clk)`
129			`begin`
130			`// read operation`
131			`raddr <= #1 addr; // read address needs to be registered to read clock`
132
133			`// write operation`
134			`if (we && ce)`
135			`mem[addr] <= #1 di;`
136			`end`
137
138			`assign #1 do = mem[raddr];`
139
140			`else
141
142			`ifdef VENDOR_XILINX
143
144			`wire [dw-1:0] q; // output from xilinx ram`
145			`//`
146			`// Instantiation of FPGA memory:`
147			`//`
148			`// Virtex/Spartan2 BlockRAMs`
149			`//`
150			`xilinx_ram_sp xilinx_ram(`
151			`.clk(clk),`
152			`.rst(rst),`
153			`.addr(addr),`
154			`.di(di),`
155			`.en(ce),`
156			`.we(we),`
157			`.do(do)`
158			`);`
159
160			`defparam`
161			`xilinx_ram.dwidth = dw,`
162			`xilinx_ram.awidth = aw;`
163
164			`else
165
166			`ifdef VENDOR_ALTERA
167
168			`//`
169			`// Instantiation of FPGA memory:`
170			`//`
171			`// Altera FLEX EABs`
172			`//`
173
174			`altera_ram_sp altera_ram(`
175			`.inclock(clk),`
176			`.address(addr),`
177			`.data(di),`
178			`.we(we && ce),`
179			`.q(do)`
180			`);`
181
182			`defparam`
183			`altera_ram.dwidth = dw,`
184			`altera_ram.awidth = aw;`
185
186			`else
187
188			`ifdef VENDOR_ARTISAN
189
190			`//`
191			`// Instantiation of ASIC memory:`
192			`//`
193			`// Artisan Synchronous Single-Port RAM (ra1sh)`
194			`//`
195			`artisan_ssp #(dw, 1<<aw, aw) artisan_ssp(`
196			`.CLK(clk),`
197			`.CEN(~ce),`
198			`.WEN(~we),`
199			`.A(addr),`
200			`.D(di),`
201			`.OEN(~oe),`
202			`.Q(do)`
203			`);`
204
205			`else
206
207			`ifdef VENDOR_AVANT
208
209			`//`
210			`// Instantiation of ASIC memory:`
211			`//`
212			`// Avant! Asynchronous Two-Port RAM`
213			`//`
214			`avant_atp avant_atp(`
215			`.web(~we),`
216			`.reb(),`
217			`.oeb(~oe),`
218			`.rcsb(),`
219			`.wcsb(),`
220			`.ra(addr),`
221			`.wa(addr),`
222			`.di(di),`
223			`.do(do)`
224			`);`
225
226			`else
227
228			`ifdef VENDOR_VIRAGE
229
230			`//`
231			`// Instantiation of ASIC memory:`
232			`//`
233			`// Virage Synchronous 1-port R/W RAM`
234			`//`
235			`virage_ssp virage_ssp(`
236			`.clk(clk),`
237			`.adr(addr),`
238			`.d(di),`
239			`.we(we),`
240			`.oe(oe),`
241			`.me(ce),`
242			`.q(do)`
243			`);`
244
245			`else
246
247			`ifdef VENDOR_VIRTUALSILICON
248
249			`//`
250			`// Instantiation of ASIC memory:`
251			`//`
252			`// Virtual Silicon Single-Port Synchronous SRAM`
253			`//`
254			`virtualsilicon_spram #(1<<aw, aw-1, dw-1) virtualsilicon_ssp(`
255			`.CK(clk),`
256			`.ADR(addr),`
257			`.DI(di),`
258			`.WEN(~we),`
259			`.CEN(~ce),`
260			`.OEN(~oe),`
261			`.DOUT(do)`
262			`);`
263
264			`else
265
266			`//`
267			`// Generic single-port synchronous RAM model`
268			`//`
269
270			`//`
271			`// Generic RAM's registers and wires`
272			`//`
273			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
274			`wire [dw-1:0] q; // RAM output`
275			`reg [aw-1:0] raddr; // RAM read address`
276			`//`
277			`// Data output drivers`
278			`//`
279			`assign do = (oe & ce) ? q : {dw{1'bz}};`
280
281			`//`
282			`// RAM read and write`
283			`//`
284
285			`// read operation`
286			`always@(posedge clk)`
287			`if (ce) // && !we)`
288			`raddr <= #1 addr; // read address needs to be registered to read clock`
289
290			`assign #1 q = rst ? {dw{1'b0}} : mem[raddr];`
291
292			`// write operation`
293			`always@(posedge clk)`
294			`if (ce && we)`
295			`mem[addr] <= #1 di;`
296
297			`// Task prints range of memory`
298			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
299			`task print_ram;`
300			`input [aw-1:0] start;`
301			`input [aw-1:0] finish;`
302			`integer rnum;`
303			`begin`
304			`for (rnum=start;rnum<=finish;rnum=rnum+1)`
305			`$display("Addr %h = %h",rnum,mem[rnum]);`
306			`end`
307			`endtask`
308
309			`endif // !VIRTUALSILICON_SSP
310			`endif // !VIRAGE_SSP
311			`endif // !AVANT_ATP
312			`endif // !ARTISAN_SSP
313			`endif // !VENDOR_ALTERA
314			`endif // !VENDOR_XILINX
315			`endif // !VENDOR_FPGA
316
317			`endmodule`
318
319
320			`//`
321			`// Black-box modules`
322			`//`
323
324			`ifdef VENDOR_ALTERA
325			`module altera_ram_sp (`
326			`address,`
327			`inclock,`
328			`we,`
329			`data,`
330			`q) /* synthesis black_box */;`
331
332			`parameter awidth = 7;`
333			`parameter dwidth = 8;`
334
335			`input [awidth -1:0] address;`
336			`input inclock;`
337			`input we;`
338			`input [dwidth -1:0] data;`
339			`output [dwidth -1:0] q;`
340
341			`// synopsis translate_off`
342			`// exemplar translate_off`
343
344			`syn_ram_irou #(`
345			`"UNUSED",`
346			`dwidth,`
347			`awidth,`
348			`1 << awidth`
349			`)`
350			`altera_spram_model (`
351			`.Inclock(inclock),`
352			`.Address(address),`
353			`.Data(data),`
354			`.WE(we),`
355			`.Q(q)`
356			`);`
357
358			`// exemplar translate_on`
359			`// synopsis translate_on`
360
361			`endmodule`
362			`endif // VENDOR_ALTERA
363
364			`ifdef VENDOR_XILINX
365			`module xilinx_ram_sp (`
366			`clk,`
367			`rst,`
368			`addr,`
369			`di,`
370			`en,`
371			`we,`
372			`do) /* synthesis black_box */ ;`
373
374			`parameter awidth = 7;`
375			`parameter dwidth = 8;`
376
377			`input clk;`
378			`input rst;`
379			`input [awidth -1:0] addr;`
380			`input [dwidth -1:0] di;`
381			`input en;`
382			`input we;`
383			`output [dwidth -1:0] do;`
384
385			`// insert simulation model`
386
387
388			`// synopsys translate_off`
389			`// exemplar translate_off`
390
391			`C_MEM_SP_BLOCK_V1_0 #(`
392			`awidth,`
393			`1,`
394			`"0",`
395			`1 << awidth,`
396			`1,`
397			`1,`
398			`1,`
399			`1,`
400			`1,`
401			`1,`
402			`1,`
403			`"",`
404			`16,`
405			`0,`
406			`0,`
407			`1,`
408			`1,`
409			`dwidth`
410			`)`
411			`xilinx_spram_model (`
412			`.CLK(clk),`
413			`.RST(rst),`
414			`.ADDR(addr),`
415			`.DI(di),`
416			`.EN(en),`
417			`.WE(we),`
418			`.DO(do)`
419			`);`
420
421			`// exemplar translate_on`
422			`// synopsys translate_on`
423
424			`endmodule`
425			`endif // VENDOR_XILINX
426