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[/] [system05/] [trunk/] [rtl/] [vhdl/] [bclrrom.vhd] - Blame information for rev 3

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1 2 dilbert57
--         FILE NAME: bclrrom.vhdl
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--       ENTITY NAME: bclr_rom
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-- ARCHITECTURE NAME: basic
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--          REVISION: A
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--
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--       DESCRIPTION: 8 byte x 8 bit ROM 
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--                    For Bit clear translations
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--
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-- Written by John Kent for the mc6805 processor
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity bclr_rom is
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  port (
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    addr   : in   std_logic_vector(2 downto 0);
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    data   : out  std_logic_vector(7 downto 0)
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  );
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end entity bclr_rom;
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architecture basic of bclr_rom is
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  constant width   : integer := 8;
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  constant memsize : integer := 8;
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  type bclr_rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
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  constant bclr_rom_data : bclr_rom_array :=
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  ( "11111110",
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    "11111101",
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    "11111011",
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    "11110111",
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    "11101111",
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    "11011111",
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    "10111111",
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    "01111111"
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         );
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begin
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   data <= bclr_rom_data(conv_integer(addr));
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end architecture basic;
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