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[/] [system05/] [trunk/] [rtl/] [vhdl/] [miniUART3.vhd] - Blame information for rev 3

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1 2 dilbert57
--===========================================================================--
2
--
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--  S Y N T H E Z I A B L E    miniUART   C O R E
4
--
5
--  www.OpenCores.Org - January 2000
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--  This core adheres to the GNU public license  
7
--
8
-- Design units   : miniUART core for the System68
9
--
10
-- File name      : miniuart2.vhd
11
--
12
-- Purpose        : Implements an miniUART device for communication purposes 
13
--                  between the CPU68 processor and the Host computer through
14
--                  an RS-232 communication protocol.
15
--                  
16
-- Dependencies   : ieee.std_logic_1164
17
--                  ieee.numeric_std
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--
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--===========================================================================--
20
-------------------------------------------------------------------------------
21
-- Revision list
22
-- Version   Author                 Date           Changes
23
--
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-- 0.1      Ovidiu Lupas     15 January 2000       New model
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-- 1.0      Ovidiu Lupas     January  2000         Synthesis optimizations
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-- 2.0      Ovidiu Lupas     April    2000         Bugs removed - RSBusCtrl
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--          the RSBusCtrl did not process all possible situations
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--
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--        olupas@opencores.org
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--
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-- 3.0      John Kent        October  2002         Changed Status bits to match mc6805
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--                                                 Added CTS, RTS, Baud rate control
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--                                                 & Software Reset
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-- 3.1      John Kent        5 January 2003        Added Word Format control a'la mc6850
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-- 3.2      John Kent        19 July 2003          Latched Data input to UART
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-- 3.3      John Kent        16 January 2004       Integrated clkunit in rxunit & txunit
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--                                                 Now has external TX 7 RX Baud Clock
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--                                                 inputs like the MC6850... 
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--                                                 also supports x1 clock and DCD. 
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--
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--        dilbert57@opencores.org
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--
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-------------------------------------------------------------------------------
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-- Entity for miniUART Unit - 9600 baudrate                                  --
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-------------------------------------------------------------------------------
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library ieee;
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   use ieee.std_logic_1164.all;
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   use ieee.numeric_std.all;
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50
entity miniUART is
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  port (
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     --
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          -- CPU signals
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          --
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     clk      : in  Std_Logic;  -- System Clock
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     rst      : in  Std_Logic;  -- Reset input (active high)
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     cs       : in  Std_Logic;  -- miniUART Chip Select
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     rw       : in  Std_Logic;  -- Read / Not Write
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     irq      : out Std_Logic;  -- Interrupt
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     Addr     : in  Std_Logic;  -- Register Select
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     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
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     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
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     --
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          -- Uart Signals
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          --
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     RxC      : in  Std_Logic;  -- Receive Baud Clock
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     TxC      : in  Std_Logic;  -- Transmit Baud Clock
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     RxD      : in  Std_Logic;  -- Receive Data
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     TxD      : out Std_Logic;  -- Transmit Data
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          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
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     CTS_n    : in  Std_Logic;  -- Clear To Send
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     RTS_n    : out Std_Logic );  -- Request To send
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end; --================== End of entity ==============================--
74
-------------------------------------------------------------------------------
75
-- Architecture for miniUART Controller Unit
76
-------------------------------------------------------------------------------
77
architecture uart of miniUART is
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  -----------------------------------------------------------------------------
79
  -- Signals
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  -----------------------------------------------------------------------------
81
  signal RxData : Std_Logic_Vector(7 downto 0); -- 
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  signal TxData : Std_Logic_Vector(7 downto 0); -- 
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  signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
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  --             StatReg detailed 
85
  -----------+--------+--------+--------+--------+--------+--------+--------+
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  --  Irq    | PErr   | ORErr  | FErr   | CTS    | DCD    | TBufE  | DRdy   |
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  -----------+--------+--------+--------+--------+--------+--------+--------+
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  signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
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  --             CtrlReg detailed 
90
  -----------+--------+--------+--------+--------+--------+--------+--------+
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  --  RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
92
  -----------+--------+--------+--------+--------+--------+--------+--------+
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  -- RxIEnb
94
  -- 0       - Rx Interrupt disabled
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  -- 1       - Rx Interrupt enabled
96
  -- TxCtl
97
  -- 0 1     - Tx Interrupt Enable
98
  -- 1 0     - RTS high
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  -- WdFmt
100
  -- 0 0 0   - 7 data, even parity, 2 stop
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  -- 0 0 1   - 7 data, odd  parity, 2 stop
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  -- 0 1 0   - 7 data, even parity, 1 stop
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  -- 0 1 1   - 7 data, odd  parity, 1 stop
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  -- 1 0 0   - 8 data, no   parity, 2 stop
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  -- 1 0 1   - 8 data, no   parity, 1 stop
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  -- 1 1 0   - 8 data, even parity, 1 stop
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  -- 1 1 1   - 8 data, odd  parity, 1 stop
108
  -- BdCtl
109
  -- 0 0     - Baud Clk divide by 1
110
  -- 0 1     - Baud Clk divide by 16
111
  -- 1 0     - Baud Clk divide by 64
112
  -- 1 1     - reset
113
 
114
  signal TxDbit   : Std_Logic;  -- Transmit data bit
115
  signal DRdy     : Std_Logic;  -- Receive Data ready
116
  signal TBufE    : Std_Logic;  -- Transmit buffer empty
117
  signal FErr     : Std_Logic;  -- Frame error
118
  signal OErr     : Std_Logic;  -- Output error
119
  signal PErr     : Std_Logic;  -- Parity Error
120
  signal TxIEnb   : Std_Logic;  -- Transmit interrupt enable
121
  signal Read     : Std_Logic;  -- Read receive buffer
122
  signal Load     : Std_Logic;  -- Load transmit buffer
123
  signal ReadCS   : Std_Logic;  -- Read Status register
124
  signal LoadCS   : Std_Logic;  -- Load Control register
125
  signal Reset    : Std_Logic;  -- Reset (Software & Hardware)
126
  signal RxRst    : Std_Logic;  -- Receive Reset (Software & Hardware)
127
  signal TxRst    : Std_Logic;  -- Transmit Reset (Software & Hardware)
128
  signal DCDDel   : Std_Logic;  -- Delayed DCD_n
129
  signal DCDEdge  : Std_Logic;  -- Rising DCD_N Edge Pulse
130
  signal DCDState : Std_Logic;  -- DCD Reset sequencer
131
  signal DCDInt   : Std_Logic;  -- DCD Interrupt
132
 
133
  -----------------------------------------------------------------------------
134
  -- Receive Unit
135
  -----------------------------------------------------------------------------
136
  component RxUnit
137
  port (
138
     Clk     : in  Std_Logic;  -- Clock signal
139
     Reset   : in  Std_Logic;  -- Reset input
140
     ReadD   : in  Std_Logic;  -- Read data signal
141
     WdFmt   : in  Std_Logic_Vector(2 downto 0); -- word format
142
     BdFmt   : in  Std_Logic_Vector(1 downto 0); -- baud format
143
     RxClk   : in  Std_Logic;  -- RS-232 clock input
144
     RxDat   : in  Std_Logic;  -- RS-232 data input
145
     FRErr   : out Std_Logic;  -- Status signal
146
     ORErr   : out Std_Logic;  -- Status signal
147
          PAErr   : out Std_logic;  -- Status signal
148
     DARdy   : out Std_Logic;  -- Status signal
149
     DAOut   : out Std_Logic_Vector(7 downto 0));
150
  end component;
151
  -----------------------------------------------------------------------------
152
  -- Transmitter Unit
153
  -----------------------------------------------------------------------------
154
  component TxUnit
155
  port (
156
     Clk    : in  Std_Logic;  -- Clock signal
157
     Reset  : in  Std_Logic;  -- Reset input
158
     LoadD  : in  Std_Logic;  -- Load transmit data
159
     DAIn   : in  Std_Logic_Vector(7 downto 0);
160
     WdFmt  : in  Std_Logic_Vector(2 downto 0); -- word format
161
     BdFmt  : in  Std_Logic_Vector(1 downto 0); -- baud format
162
     TxClk  : in  Std_Logic;  -- Enable input
163
     TxDat  : out Std_Logic;  -- RS-232 data output
164
     TBE    : out Std_Logic );  -- Tx buffer empty
165
  end component;
166
begin
167
  -----------------------------------------------------------------------------
168
  -- Instantiation of internal components
169
  -----------------------------------------------------------------------------
170
 
171
  RxDev   : RxUnit  port map (
172
                Clk      => clk,
173
                                         Reset    => RxRst,
174
                                         ReadD    => Read,
175
                                         WdFmt    => CtrlReg(4 downto 2),
176
                                         BdFmt    => CtrlReg(1 downto 0),
177
                                         RxClk    => RxC,
178
                                         RxDat    => RxD,
179
                                         FRErr    => FErr,
180
                                         ORErr    => OErr,
181
                                         PAErr    => PErr,
182
                                         DARdy    => DRdy,
183
                                         DAOut    => RxData
184
                                         );
185
 
186
 
187
  TxDev   : TxUnit  port map (
188
                Clk      => clk,
189
                                         Reset    => TxRst,
190
                                         LoadD    => Load,
191
                                         DAIn     => TxData,
192
                                         WdFmt    => CtrlReg(4 downto 2),
193
                                         BdFmt    => CtrlReg(1 downto 0),
194
                                         TxClk    => TxC,
195
                                         TxDat    => TxDbit,
196
                                         TBE      => TBufE
197
                                         );
198
 
199
  -----------------------------------------------------------------------------
200
  -- Implements the controller for Rx&Tx units
201
  -----------------------------------------------------------------------------
202
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
203
                          DRdy, TBufE, DCD_n, CTS_n, DCDInt,
204
                          FErr, OErr,  PErr )
205
variable Int : Std_Logic;
206
  begin
207
    if Reset = '1' then
208
            Int     := '0';
209
       StatReg <= "00000000";
210
                 irq     <= '0';
211
    elsif clk'event and clk='0' then
212
                 Int        := (CtrlReg(7) and DRdy)   or
213
                               (CtrlReg(7) and DCDInt) or
214
                               (TxIEnb     and TBufE);
215
       StatReg(0) <= DRdy;  -- Receive Data Ready
216
       StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
217
            StatReg(2) <= DCDInt; -- Data Carrier Detect
218
                 StatReg(3) <= CTS_n; -- Clear To Send
219
       StatReg(4) <= FErr;  -- Framing error
220
       StatReg(5) <= OErr;  -- Overrun error
221
       StatReg(6) <= PErr;  -- Parity error
222
                 StatReg(7) <= Int;
223
                 irq        <= Int;
224
    end if;
225
  end process;
226
 
227
 
228
-----------------------------------------------------------------------------
229
-- Transmit control
230
-----------------------------------------------------------------------------
231
 
232
miniUart_TxControl : process( CtrlReg, TxDbit )
233
begin
234
    case CtrlReg(6 downto 5) is
235
         when "00" => -- Disable TX Interrupts, Assert RTS
236
           RTS_n  <= '0';
237
                TxIEnb <= '0';
238
                TxD    <= TxDbit;
239
    when "01" => -- Enable TX interrupts, Assert RTS
240
           RTS_n  <= '0';
241
                TxIEnb <= '1';
242
                TxD    <= TxDbit;
243
    when "10" => -- Disable Tx Interrupts, Clear RTS
244
           RTS_n  <= '1';
245
                TxIEnb <= '0';
246
                TxD    <= TxDbit;
247
    when "11" => -- Disable Tx interrupts, Assert RTS, send break
248
           RTS_n  <= '0';
249
                TxIEnb <= '0';
250
                TxD    <= '0';
251
    when others =>
252
           RTS_n  <= '0';
253
                TxIEnb <= '0';
254
                TxD    <= TxDbit;
255
         end case;
256
end process;
257
 
258
-----------------------------------------------------------------------------
259
-- Write to control register
260
-----------------------------------------------------------------------------
261
 
262
miniUart_Control:  process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
263
begin
264
  if (reset = '1') then
265
                 TxData  <= "00000000";
266
                 Load    <= '0';
267
                 Read    <= '0';
268
            CtrlReg <= "00000000";
269
                 LoadCS  <= '0';
270
                 ReadCS <= '0';
271
        elsif clk'event and clk='0' then
272
            if cs = '1' then
273
              if Addr = '1' then        -- Data Register
274
                     if rw = '0' then   -- write data register
275
             TxData <= DataIn;
276
                  Load   <= '1';
277
                       Read   <= '0';
278
                else               -- read Data Register
279
             TxData <= TxData;
280
                  Load   <= '0';
281
             Read   <= '1';
282
                          end if; -- rw
283
                     CtrlReg <= CtrlReg;
284
                          LoadCS  <= '0';
285
                          ReadCS         <= '0';
286
              else                                        -- Control / Status register
287
           TxData <= TxData;
288
                Load   <= '0';
289
                     Read   <= '0';
290
                     if rw = '0' then   -- write control register
291
                            CtrlReg <= DataIn;
292
                                 LoadCS  <= '1';
293
                                 ReadCS <= '0';
294
                else               -- read status Register
295
                       CtrlReg <= CtrlReg;
296
                                 LoadCS  <= '0';
297
                                 ReadCS <= '1';
298
                          end if; -- rw
299
                   end if; -- Addr
300
            else                   -- not selected
301
         TxData  <= TxData;
302
              Load    <= '0';
303
                   Read    <= '0';
304
                        CtrlReg <= CtrlReg;
305
                        LoadCS  <= '0';
306
                        ReadCS  <= '0';
307
 
308
            end if;  -- cs
309
   end if; -- clk / reset
310
end process;
311
 
312
---------------------------------------------------------------
313
--
314
-- set data output mux
315
--
316
--------------------------------------------------------------
317
 
318
miniUart_data_read: process(Addr, StatReg, RxData)
319
begin
320
          if Addr = '1' then
321
                 DataOut <= RxData;    -- read data register
322
          else
323
                 DataOut <= StatReg;   -- read status register
324
          end if; -- Addr
325
end process;
326
 
327
 
328
---------------------------------------------------------------
329
--
330
-- Data Carrier Detect Edge rising edge detect
331
--
332
---------------------------------------------------------------
333
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel  )
334
begin
335
   if reset = '1' then
336
           DCDEdge <= '0';
337
                DCDDel  <= '0';
338
   elsif clk'event and clk = '0' then
339
           DCDDel <= DCD_n;
340
                DCDEdge <= DCD_n and (not DCDDel);
341
   end if;
342
end process;
343
 
344
 
345
---------------------------------------------------------------
346
--
347
-- Data Carrier Detect Interrupt
348
--
349
---------------------------------------------------------------
350
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
351
begin
352
   if reset = '1' then
353
           DCDInt   <= '0';
354
                DCDState <= '0';
355
   elsif clk'event and clk = '0' then
356
                if DCDEdge = '1' then
357
                   DCDInt   <= '1';
358
                        DCDState <= '0';
359
      elsif DCDState    = '0' then
360
                     -- To reset DCD interrupt, First read status
361
                          if (ReadCS <= '1') and (DCDInt = '1') then
362
                             DCDState <= '1';
363
           else
364
                             DCDState <= '0';
365
           end if;
366
                     DCDInt <= DCDInt;
367
      else      -- DCDstate = '1'
368
                     -- Then read the data register
369
                          if Read <= '1' then
370
                             DCDState <= '0';
371
                                  DCDInt <= '0';
372
           else
373
                             DCDState <= DCDState;
374
                                  DCDInt   <= DCDInt;
375
           end if;
376
      end if; -- DCDState
377
   end if; -- clk / reset
378
end process;
379
 
380
---------------------------------------------------------------
381
--
382
-- reset may be hardware or software
383
--
384
---------------------------------------------------------------
385
 
386
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
387
begin
388
          Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
389
          TxRst <= Reset;
390
          RxRst <= Reset or DCD_n;
391
end process;
392
 
393
end; --===================== End of architecture =======================--
394
 

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