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[/] [systemc_cordic/] [trunk/] [cordic_ip/] [cordic.h] - Blame information for rev 4

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1 3 wwcheng
// cordic.h: header file
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/********************************************************************
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//
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// Module:
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//   Cordic Engine Pipeline Stage
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//
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// Interface:
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//   Registered input, non-registered output
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//
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//
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// Authors:     Winnie Cheng <wwcheng@stanford.edu>,
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//              Peter Wu <peter5@stanford.edu>
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//
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 *********************************************************************/
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#include "systemc.h"
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#include "opcode.h"
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SC_MODULE(cordic) {
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    // Clock Declaration
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    sc_in_clk clk;
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    // Input ports Declaration
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    sc_in<bool> start;          // enables the stage
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    sc_in<bool> reset;
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    // Input data - previous stage results
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    sc_in<short> in_x;
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    sc_in<short> in_y;
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    sc_in<short> in_acc_phase;
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    // Input data - propagated instruction info
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    sc_in<sc_uint<UNIT_SEL_WIDTH> > in_opcode;
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    sc_in<short> in_desired_phase;
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    // Input data - stage parametrization
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    sc_in<short> stage_num;
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    sc_in<short> tablep;
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    sc_in<short> tableh;
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    // Output ports Declaration
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    sc_out<bool> done;
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    // Output data - results of this stage
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    sc_out<short> out_x;
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    sc_out<short> out_y;
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    sc_out<short> out_acc_phase;
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    // Output data - propagated instruction info 
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    sc_out<sc_uint<UNIT_SEL_WIDTH> > out_opcode;
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    sc_out<short> out_desired_phase;
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    // Declare implementation functions
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    void cordic_process();
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    // Constructor
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    SC_CTOR(cordic)
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    {
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        // Register processes and define active clock edge
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        SC_CTHREAD(cordic_process, clk.pos());
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        // Watching for global reset
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        watching(reset.delayed()==true);
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    }
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}; // end module cordic 

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