OpenCores
URL https://opencores.org/ocsvn/systemc_cordic/systemc_cordic/trunk

Subversion Repositories systemc_cordic

[/] [systemc_cordic/] [trunk/] [cordic_ip/] [design.htm] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 wwcheng 
<HTML>
2 
<HEAD><TITLE>SystemC CORDIC design</TITLE></HEAD>
3 
 
4 
<BODY BGCOLOR=white>
5 
<H2><B>SystemC CORDIC design</B></H2>
6 
Team Members:<br><br>
7 
Winnie Cheng (wwcheng@stanfordalumni.org)<br>
8 
Peter Wu (peter5@stanford.edu)<br>
9 
<br>
10 
<H3><I>Overview</I></H3>
11 
CORDIC stands for <B>CO</B>ordinate <B>R</B>otation <B>DI</B>gital <B>C</B>omputer. It is an inexpensive way of performing some vector-based and trignometric computations. CORDIC revolves around the idea of rotation. It is particularly useful in designs where multipliers are not available. CORDIC computes values based on rotating vectors by powers of 2, therefore, only simple shifters and adders are needed. In addition, the iterative nature of the algorithm lends itself to an efficient pipeline implementation.<BR><BR>
12 
<BR>
13 
 
14 
<H3><I>Design Functionalities</I></H3>
15 
We have decided to support the following features in our CORDIC implementation:<BR><BR>
16 
<li>computes rotate(x, y, angle)</li>
17 
<li>computes magnitude(x, y)</li>
18 
<li>computes phase(x, y)</li>
19 
<li>computes sin(angle)</li>
20 
<li>computes cos(angle)</li>
21 
<li>computes sinh(angle)</li>
22 
<li>computes cosh(angle)</li>
23 
<li>14-stage fully pipelined design</li>
24 
<li>power-save detection on pipeline - pipeline shuts off when certain number of idle cycles have elapsed</li>
25 
<BR>
26 
<BR>
27 
<BR>
28 
<H3><I>Design Interface</I></H3>
29 
Our CORDIC core consists of the following blocks:<br><br>
30 
<li>Instruction Decoding Unit (decoder)</li>
31 
<li>CORDIC 12-stage pipeline (cordpipe - encapsulates 12 instances of basic cordic unit)</li>
32 
<li>Pipeline Output Adjustment Unit (adjust)</li>
33 
<br><br>
34 
<pre>
35 
            _________     __________________________________     __________
36 
           |         |   |  ________   cordpipe   ________  |   |          |
37 
   opcode->|         |   | |        |            |        | |   |          |->out_opcode
38 
           |         |   | |        |            |        | |   |          |
39 
 operand1->| decoder |<->| | cordic |   ......   | cordic | |<->|  adjust  |->result1
40 
 operand2->| (1-stg) |   | |  (s0)  | 12 stages  |  (s11) | |   |  (1-stg) |->result2
41 
 operand3->|         |   | |        |            |        | |   |          |
42 
           |         |   | |________|            |________| |   |          |
43 
           |_________|   |__________________________________|   |__________|
44 
 
45 
</pre>
46 
The CORDIC core accepts an instruction at the decoder interface. The Decoder module interprets the instruction type, performs pre-computation on the operands and sets up the pipeline to handle the instruction accordingly. The Decoder module has a latency of one cycle. Next, the pipeline unit is activated. It is a 12-stage pipeline consisting of identical submodules called "cordic" that have been parametrized accordingly to their location in the pipeline. When processing reaches the end of the pipeline, the "adjust" module performs some post-computation according to the instruction type and outputs the result. The Adjust module has a latency of one cycle. Therefore, the latency of the core is 14 cycles.<BR>
47 
<BR>
48 
<b>Inputs:</b>
49 
<pre>
50 
- clock (1-bit): system clock
51 
- reset (1-bit): system reset
52 
- start (1-bit): enables CORDIC unit
53 
- instruction_valid (1-bit): indicates input instruction is valid
54 
- opcode (4-bit): instruction opcode indicates which operation to feed into pipeline
55 
- operand1 (16-bit): instruction operand (fixed-point representation)
56 
- operand2 (16-bit): instruction operand (fixed-point representation)
57 
- operand3 (16-bit): instruction operand (fixed-point representation)
58 
</pre>
59 
<b>Outputs:</b>
60 
<pre>
61 
- result_valid (1-bit): indicates result at end of pipeline is valid
62 
- out_opcode (4-bit): associated opcode for result at end of pipeline
63 
- out_result1 (16-bit): output result1 at end of pipeline (fixed-point representation)
64 
- out_result2 (16-bit): output result2 at end of pipeline (fixed-point representation)
65 
</pre>
66 
<b>Instruction Format:</b>
67 
<pre>
68 
(1) Rotate function
69 
        syntax: rot x y a
70 
        arguments:
71 
                operand1 - original x-coordinate of vector
72 
                operand2 - original y-coordinate of vector
73 
                operand3 - angle in deg to rotate original vector by
74 
        return values:
75 
                result1 - x-coordinate of vector rotated by angle a
76 
                result2 - y-coordinate of vector rotated by angle a
77 
 
78 
(2) Magnitude-and-Phase function
79 
        syntax: mgp x y
80 
        arguments:
81 
                operand1 - x-coordinate of vector
82 
                operand2 - y-coordinate of vector
83 
        return values:
84 
                result1 - magnitude of vector(x,y)
85 
                result2 - phase of vector(x,y)
86 
 
87 
(3) Sin-and-Cos function
88 
        syntax: sin a
89 
                cos b
90 
        arguments:
91 
                operand1 - angle in deg
92 
        return values:
93 
                result1 - sine of angle a
94 
                result2 - cosine of angle a
95 
 
96 
(4) Sinh-and-Cosh function
97 
        syntax: sinh a
98 
                cosh a
99 
        arguments:
100 
                operand1 - angle in deg
101 
        return values:
102 
                result1 - sinh of angle a
103 
                result2 - cosh of angle a
104 
 
105 
</pre>
106 
 
107 
<BR>
108 
<H3><I>Testbench</I></H3>
109 
The testbench is described in the "testbench" module and the "monitor" module. The testbench supports a user defined instruction file that adheres to the syntax of the instruction format. It also supports the generation of random inputs. It uses the C math libraries to compute expected values to verify results at runtime. The testbench executes the following tests:<br><br>
110 
<li>random inputs to exercise large test set on rotate function</li>
111 
<li>random inputs to exercise large test set on magnitude and phase functions</li>
112 
<li>random inputs to exercise large test set on sin and cos functions</li>
113 
<li>random inputs to exercise large test set on sinh and cosh functions</li>
114 
<li>pipeline operated as non-pipelined mode (NOP stalls)</li>
115 
<li>fully pipelined mode with interleaved user defined instructions</li>
116 
<li>idle period to test pipeline power-save activation</li>
117 
<BR><BR>
118 
<hr>
119 
<H5><I>May 25, 2003</I></H5>
120 
</BODY>
121 
</HTML>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.