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[/] [systemc_rng/] [trunk/] [bench/] [verilog/] [top.v] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  RNG main simulation file                                    ////
////                                                              ////
////  This file is part of the SystemC RNG                        ////
////                                                              ////
////  Description:                                                ////
////  RNG main simulation file                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - done                                                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, javier.castillo@urjc.es              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/09/23 09:45:06  jcastillo
// Verilog first import
//
 
`timescale 10ns/1ns
 
module top;
 
 
reg clk;
reg reset;
reg loadseed_i;
 
reg [31:0] seed_i;
wire [31:0] number_o;
 
rng r1(clk,reset,loadseed_i,seed_i,number_o);
 
   initial
 
   begin
     clk = 1'b1;
     reset = 1'b1;
     loadseed_i = 1'b0;
     seed_i=32'h12345678;
     @(posedge clk);
     reset = #1 1'b0;
     @(posedge clk);
     reset = #1 1'b1;
     @(posedge clk);
         loadseed_i = #1 1'b1;
         @(posedge clk);
         loadseed_i = #1 1'b0;
 
         while(1)
         begin
           @(posedge clk);
       $display("%H",number_o);
         end
 
 
     $finish;
 
   end
 
   always #5 clk = !clk;
 
endmodule

Line No.	Rev	Author	Line
1	7	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// RNG main simulation file ////`
4			`//// ////`
5			`//// This file is part of the SystemC RNG ////`
6			`//// ////`
7			`//// Description: ////`
8			`//// RNG main simulation file ////`
9			`//// ////`
10			`//// To Do: ////`
11			`//// - done ////`
12			`//// ////`
13			`//// Author(s): ////`
14	11	jcastillo	`//// - Javier Castillo, javier.castillo@urjc.es ////`
15	7	jcastillo	`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	11	jcastillo	`// Revision 1.1 2004/09/23 09:45:06 jcastillo`
47			`// Verilog first import`
48			`//`
49	7	jcastillo
50			`timescale 10ns/1ns
51
52			`module top;`
53
54
55			`reg clk;`
56			`reg reset;`
57			`reg loadseed_i;`
58
59			`reg [31:0] seed_i;`
60			`wire [31:0] number_o;`
61
62			`rng r1(clk,reset,loadseed_i,seed_i,number_o);`
63
64			`initial`
65
66			`begin`
67			`clk = 1'b1;`
68			`reset = 1'b1;`
69			`loadseed_i = 1'b0;`
70			`seed_i=32'h12345678;`
71			`@(posedge clk);`
72			`reset = #1 1'b0;`
73			`@(posedge clk);`
74			`reset = #1 1'b1;`
75			`@(posedge clk);`
76			`loadseed_i = #1 1'b1;`
77			`@(posedge clk);`
78			`loadseed_i = #1 1'b0;`
79
80			`while(1)`
81			`begin`
82			`@(posedge clk);`
83			`$display("%H",number_o);`
84			`end`
85
86
87			`$finish;`
88
89			`end`
90
91			`always #5 clk = !clk;`
92
93			`endmodule`

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[/] [systemc_rng/] [trunk/] [bench/] [verilog/] [top.v] - Blame information for rev 12