OpenCores
URL https://opencores.org/ocsvn/systemc_rng/systemc_rng/trunk

Subversion Repositories systemc_rng

[/] [systemc_rng/] [trunk/] [bench/] [verilog/] [top.v] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 jcastillo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  RNG main simulation file                                    ////
4
////                                                              ////
5
////  This file is part of the SystemC RNG                        ////
6
////                                                              ////
7
////  Description:                                                ////
8
////  RNG main simulation file                                    ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - done                                                     ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Javier Castillo, jcastilo@opencores.org               ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46
 
47
`timescale 10ns/1ns
48
 
49
module top;
50
 
51
 
52
reg clk;
53
reg reset;
54
reg loadseed_i;
55
 
56
reg [31:0] seed_i;
57
wire [31:0] number_o;
58
 
59
rng r1(clk,reset,loadseed_i,seed_i,number_o);
60
 
61
   initial
62
 
63
   begin
64
     clk = 1'b1;
65
     reset = 1'b1;
66
     loadseed_i = 1'b0;
67
     seed_i=32'h12345678;
68
     @(posedge clk);
69
     reset = #1 1'b0;
70
     @(posedge clk);
71
     reset = #1 1'b1;
72
     @(posedge clk);
73
         loadseed_i = #1 1'b1;
74
         @(posedge clk);
75
         loadseed_i = #1 1'b0;
76
 
77
         while(1)
78
         begin
79
           @(posedge clk);
80
       $display("%H",number_o);
81
         end
82
 
83
 
84
     $finish;
85
 
86
   end
87
 
88
   always #5 clk = !clk;
89
 
90
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.