OpenCores
URL https://opencores.org/ocsvn/systemc_rng/systemc_rng/trunk

Subversion Repositories systemc_rng

[/] [systemc_rng/] [trunk/] [rtl/] [systemc/] [stimulus.cpp] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jcastillo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Random Number Generator Testbench                           ////
4
////                                                              ////
5
////  This file is part of the SystemC RNG project                ////
6
////                                                              ////
7
////  Description:                                                ////
8
////  Testbench stimulus                                          ////
9
////                                                              ////
10
////  To Do:                                                      ////
11
////   - nothing                                                  ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14 11 jcastillo
////      - Javier Castillo, javier.castillo@urjc.es              ////
15 2 jcastillo
////                                                              ////
16 11 jcastillo
////  This core is provided by Universidad Rey Juan Carlos        ////
17
////  http://www.escet.urjc.es/~jmartine                          ////
18 2 jcastillo
////                                                              ////
19
//////////////////////////////////////////////////////////////////////
20
////                                                              ////
21
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
22
////                                                              ////
23
//// This source file may be used and distributed without         ////
24
//// restriction provided that this copyright statement is not    ////
25
//// removed from the file and that any derivative work contains  ////
26
//// the original copyright notice and the associated disclaimer. ////
27
////                                                              ////
28
//// This source file is free software; you can redistribute it   ////
29
//// and/or modify it under the terms of the GNU Lesser General   ////
30
//// Public License as published by the Free Software Foundation; ////
31
//// either version 2.1 of the License, or (at your option) any   ////
32
//// later version.                                               ////
33
////                                                              ////
34
//// This source is distributed in the hope that it will be       ////
35
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
36
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
37
//// PURPOSE.  See the GNU Lesser General Public License for more ////
38
//// details.                                                     ////
39
////                                                              ////
40
//// You should have received a copy of the GNU Lesser General    ////
41
//// Public License along with this source; if not, download it   ////
42
//// from http://www.opencores.org/lgpl.shtml                     ////
43
////                                                              ////
44
//////////////////////////////////////////////////////////////////////
45
//
46
// CVS Revision History
47
//
48
// $Log: not supported by cvs2svn $
49 11 jcastillo
// Revision 1.2  2004/08/30 17:01:50  jcastillo
50
// Used indent command
51
//
52 6 jcastillo
// Revision 1.1.1.1  2004/08/19 14:27:14  jcastillo
53
// First import
54
//
55 2 jcastillo
 
56
#include "systemc.h"
57
#include "stimulus.h"
58 6 jcastillo
 
59
void
60
stimulus::tb ()
61
{
62
 
63
  wait (clk->posedge_event ());
64
  reset.write (0);
65
  wait (clk->posedge_event ());
66
  reset.write (1);
67
  wait (clk->posedge_event ());
68
  loadseed_o.write (1);
69
  seed_o.write (0x12678);
70
  wait (clk->posedge_event ());
71
  loadseed_o.write (0);
72
  for (;;)
73
    {
74
      wait (clk->posedge_event ());
75
      cout << (unsigned int) number_i.read () << endl;
76
    }
77
 
78
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.