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[/] [systemc_rng/] [trunk/] [rtl/] [verilog/] [rng.v] - Blame information for rev 10

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Random Number Generator                                     ////
////                                                              ////
////  This file is part of the SystemC RNG                        ////
////                                                              ////
////  Description:                                                ////
////                                                              ////
////  Implementation of random number generator                   ////
////                                                              ////
////  To Do:                                                      ////
////   - done                                                     ////
////                                                              ////
////  Author(s):                                                  ////
////   - Javier Castillo, jcastilo@opencores.org                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2005/07/29 09:13:06  jcastillo
// Correct bit 28 of CASR
//
// Revision 1.1  2004/09/23 09:43:06  jcastillo
// Verilog first import
//
 
`timescale 10ns/1ns
 
module rng(clk,reset,loadseed_i,seed_i,number_o);
input clk;
input reset;
input loadseed_i;
input [31:0] seed_i;
output [31:0] number_o;
 
reg [31:0] number_o;
 
reg [42:0] LFSR_reg;
reg [36:0] CASR_reg;
 
 
//CASR:
reg[36:0] CASR_varCASR,CASR_outCASR;
always @(posedge clk or negedge reset)
 
   begin
 
 
 
 
   if (!reset )
 
      begin
 
      CASR_reg  = (1);
 
      end
 
   else
 
      begin
 
      if (loadseed_i )
 
         begin
 
         CASR_varCASR [36:32]=0;
         CASR_varCASR [31:0]=seed_i ;
         CASR_reg  = (CASR_varCASR );
 
 
         end
 
      else
 
         begin
 
         CASR_varCASR =CASR_reg ;
 
         CASR_outCASR [36]=CASR_varCASR [35]^CASR_varCASR [0];
         CASR_outCASR [35]=CASR_varCASR [34]^CASR_varCASR [36];
         CASR_outCASR [34]=CASR_varCASR [33]^CASR_varCASR [35];
         CASR_outCASR [33]=CASR_varCASR [32]^CASR_varCASR [34];
         CASR_outCASR [32]=CASR_varCASR [31]^CASR_varCASR [33];
         CASR_outCASR [31]=CASR_varCASR [30]^CASR_varCASR [32];
         CASR_outCASR [30]=CASR_varCASR [29]^CASR_varCASR [31];
         CASR_outCASR [29]=CASR_varCASR [28]^CASR_varCASR [30];
         CASR_outCASR [28]=CASR_varCASR [27]^CASR_varCASR [29];
         CASR_outCASR [27]=CASR_varCASR [26]^CASR_varCASR [27]^CASR_varCASR [28];
         CASR_outCASR [26]=CASR_varCASR [25]^CASR_varCASR [27];
         CASR_outCASR [25]=CASR_varCASR [24]^CASR_varCASR [26];
         CASR_outCASR [24]=CASR_varCASR [23]^CASR_varCASR [25];
         CASR_outCASR [23]=CASR_varCASR [22]^CASR_varCASR [24];
         CASR_outCASR [22]=CASR_varCASR [21]^CASR_varCASR [23];
         CASR_outCASR [21]=CASR_varCASR [20]^CASR_varCASR [22];
         CASR_outCASR [20]=CASR_varCASR [19]^CASR_varCASR [21];
         CASR_outCASR [19]=CASR_varCASR [18]^CASR_varCASR [20];
         CASR_outCASR [18]=CASR_varCASR [17]^CASR_varCASR [19];
         CASR_outCASR [17]=CASR_varCASR [16]^CASR_varCASR [18];
         CASR_outCASR [16]=CASR_varCASR [15]^CASR_varCASR [17];
         CASR_outCASR [15]=CASR_varCASR [14]^CASR_varCASR [16];
         CASR_outCASR [14]=CASR_varCASR [13]^CASR_varCASR [15];
         CASR_outCASR [13]=CASR_varCASR [12]^CASR_varCASR [14];
         CASR_outCASR [12]=CASR_varCASR [11]^CASR_varCASR [13];
         CASR_outCASR [11]=CASR_varCASR [10]^CASR_varCASR [12];
         CASR_outCASR [10]=CASR_varCASR [9]^CASR_varCASR [11];
         CASR_outCASR [9]=CASR_varCASR [8]^CASR_varCASR [10];
         CASR_outCASR [8]=CASR_varCASR [7]^CASR_varCASR [9];
         CASR_outCASR [7]=CASR_varCASR [6]^CASR_varCASR [8];
         CASR_outCASR [6]=CASR_varCASR [5]^CASR_varCASR [7];
         CASR_outCASR [5]=CASR_varCASR [4]^CASR_varCASR [6];
         CASR_outCASR [4]=CASR_varCASR [3]^CASR_varCASR [5];
         CASR_outCASR [3]=CASR_varCASR [2]^CASR_varCASR [4];
         CASR_outCASR [2]=CASR_varCASR [1]^CASR_varCASR [3];
         CASR_outCASR [1]=CASR_varCASR [0]^CASR_varCASR [2];
         CASR_outCASR [0]=CASR_varCASR [36]^CASR_varCASR [1];
 
         CASR_reg  = (CASR_outCASR );
 
         end
 
 
      end
 
 
   end
//LFSR:
reg[42:0] LFSR_varLFSR;
reg outbitLFSR;
always @(posedge clk or negedge reset)
 
   begin
 
 
   if (!reset )
 
      begin
 
      LFSR_reg  = (1);
 
      end
 
   else
 
      begin
 
      if (loadseed_i )
 
         begin
 
         LFSR_varLFSR [42:32]=0;
         LFSR_varLFSR [31:0]=seed_i ;
         LFSR_reg  = (LFSR_varLFSR );
 
 
         end
 
      else
 
         begin
 
         LFSR_varLFSR =LFSR_reg ;
 
         outbitLFSR =LFSR_varLFSR [42];
         LFSR_varLFSR [42]=LFSR_varLFSR [41];
         LFSR_varLFSR [41]=LFSR_varLFSR [40]^outbitLFSR ;
         LFSR_varLFSR [40]=LFSR_varLFSR [39];
         LFSR_varLFSR [39]=LFSR_varLFSR [38];
         LFSR_varLFSR [38]=LFSR_varLFSR [37];
         LFSR_varLFSR [37]=LFSR_varLFSR [36];
         LFSR_varLFSR [36]=LFSR_varLFSR [35];
         LFSR_varLFSR [35]=LFSR_varLFSR [34];
         LFSR_varLFSR [34]=LFSR_varLFSR [33];
         LFSR_varLFSR [33]=LFSR_varLFSR [32];
         LFSR_varLFSR [32]=LFSR_varLFSR [31];
         LFSR_varLFSR [31]=LFSR_varLFSR [30];
         LFSR_varLFSR [30]=LFSR_varLFSR [29];
         LFSR_varLFSR [29]=LFSR_varLFSR [28];
         LFSR_varLFSR [28]=LFSR_varLFSR [27];
         LFSR_varLFSR [27]=LFSR_varLFSR [26];
         LFSR_varLFSR [26]=LFSR_varLFSR [25];
         LFSR_varLFSR [25]=LFSR_varLFSR [24];
         LFSR_varLFSR [24]=LFSR_varLFSR [23];
         LFSR_varLFSR [23]=LFSR_varLFSR [22];
         LFSR_varLFSR [22]=LFSR_varLFSR [21];
         LFSR_varLFSR [21]=LFSR_varLFSR [20];
         LFSR_varLFSR [20]=LFSR_varLFSR [19]^outbitLFSR ;
         LFSR_varLFSR [19]=LFSR_varLFSR [18];
         LFSR_varLFSR [18]=LFSR_varLFSR [17];
         LFSR_varLFSR [17]=LFSR_varLFSR [16];
         LFSR_varLFSR [16]=LFSR_varLFSR [15];
         LFSR_varLFSR [15]=LFSR_varLFSR [14];
         LFSR_varLFSR [14]=LFSR_varLFSR [13];
         LFSR_varLFSR [13]=LFSR_varLFSR [12];
         LFSR_varLFSR [12]=LFSR_varLFSR [11];
         LFSR_varLFSR [11]=LFSR_varLFSR [10];
         LFSR_varLFSR [10]=LFSR_varLFSR [9];
         LFSR_varLFSR [9]=LFSR_varLFSR [8];
         LFSR_varLFSR [8]=LFSR_varLFSR [7];
         LFSR_varLFSR [7]=LFSR_varLFSR [6];
         LFSR_varLFSR [6]=LFSR_varLFSR [5];
         LFSR_varLFSR [5]=LFSR_varLFSR [4];
         LFSR_varLFSR [4]=LFSR_varLFSR [3];
         LFSR_varLFSR [3]=LFSR_varLFSR [2];
         LFSR_varLFSR [2]=LFSR_varLFSR [1];
         LFSR_varLFSR [1]=LFSR_varLFSR [0]^outbitLFSR ;
         LFSR_varLFSR [0]=LFSR_varLFSR [42];
 
         LFSR_reg  = (LFSR_varLFSR );
 
         end
 
 
      end
 
 
   end
//combinate:
always @(posedge clk or negedge reset)
 
   begin
 
   if (!reset )
 
      begin
 
      number_o  = (0);
 
      end
 
   else
 
      begin
 
      number_o  = (LFSR_reg [31:0]^CASR_reg[31:0]);
 
      end
 
 
   end
 
endmodule

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Subversion Repositories systemc_rng

[/] [systemc_rng/] [trunk/] [rtl/] [verilog/] [rng.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	7	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Random Number Generator ////`
4			`//// ////`
5			`//// This file is part of the SystemC RNG ////`
6			`//// ////`
7			`//// Description: ////`
8			`//// ////`
9			`//// Implementation of random number generator ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - done ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Javier Castillo, jcastilo@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	10	jcastillo	`// Revision 1.2 2005/07/29 09:13:06 jcastillo`
48			`// Correct bit 28 of CASR`
49			`//`
50	9	jcastillo	`// Revision 1.1 2004/09/23 09:43:06 jcastillo`
51			`// Verilog first import`
52			`//`
53	7	jcastillo
54			`timescale 10ns/1ns
55
56			`module rng(clk,reset,loadseed_i,seed_i,number_o);`
57			`input clk;`
58			`input reset;`
59			`input loadseed_i;`
60			`input [31:0] seed_i;`
61			`output [31:0] number_o;`
62
63			`reg [31:0] number_o;`
64
65			`reg [42:0] LFSR_reg;`
66			`reg [36:0] CASR_reg;`
67
68
69			`//CASR:`
70			`reg[36:0] CASR_varCASR,CASR_outCASR;`
71			`always @(posedge clk or negedge reset)`
72
73			`begin`
74
75
76
77
78			`if (!reset )`
79
80			`begin`
81
82			`CASR_reg = (1);`
83
84			`end`
85
86			`else`
87
88			`begin`
89
90			`if (loadseed_i )`
91
92			`begin`
93
94	10	jcastillo	`CASR_varCASR [36:32]=0;`
95	7	jcastillo	`CASR_varCASR [31:0]=seed_i ;`
96			`CASR_reg = (CASR_varCASR );`
97
98
99			`end`
100
101			`else`
102
103			`begin`
104
105			`CASR_varCASR =CASR_reg ;`
106
107			`CASR_outCASR [36]=CASR_varCASR [35]^CASR_varCASR [0];`
108			`CASR_outCASR [35]=CASR_varCASR [34]^CASR_varCASR [36];`
109			`CASR_outCASR [34]=CASR_varCASR [33]^CASR_varCASR [35];`
110			`CASR_outCASR [33]=CASR_varCASR [32]^CASR_varCASR [34];`
111			`CASR_outCASR [32]=CASR_varCASR [31]^CASR_varCASR [33];`
112			`CASR_outCASR [31]=CASR_varCASR [30]^CASR_varCASR [32];`
113			`CASR_outCASR [30]=CASR_varCASR [29]^CASR_varCASR [31];`
114			`CASR_outCASR [29]=CASR_varCASR [28]^CASR_varCASR [30];`
115	10	jcastillo	`CASR_outCASR [28]=CASR_varCASR [27]^CASR_varCASR [29];`
116			`CASR_outCASR [27]=CASR_varCASR [26]^CASR_varCASR [27]^CASR_varCASR [28];`
117	7	jcastillo	`CASR_outCASR [26]=CASR_varCASR [25]^CASR_varCASR [27];`
118			`CASR_outCASR [25]=CASR_varCASR [24]^CASR_varCASR [26];`
119			`CASR_outCASR [24]=CASR_varCASR [23]^CASR_varCASR [25];`
120			`CASR_outCASR [23]=CASR_varCASR [22]^CASR_varCASR [24];`
121			`CASR_outCASR [22]=CASR_varCASR [21]^CASR_varCASR [23];`
122			`CASR_outCASR [21]=CASR_varCASR [20]^CASR_varCASR [22];`
123			`CASR_outCASR [20]=CASR_varCASR [19]^CASR_varCASR [21];`
124			`CASR_outCASR [19]=CASR_varCASR [18]^CASR_varCASR [20];`
125			`CASR_outCASR [18]=CASR_varCASR [17]^CASR_varCASR [19];`
126			`CASR_outCASR [17]=CASR_varCASR [16]^CASR_varCASR [18];`
127			`CASR_outCASR [16]=CASR_varCASR [15]^CASR_varCASR [17];`
128			`CASR_outCASR [15]=CASR_varCASR [14]^CASR_varCASR [16];`
129			`CASR_outCASR [14]=CASR_varCASR [13]^CASR_varCASR [15];`
130			`CASR_outCASR [13]=CASR_varCASR [12]^CASR_varCASR [14];`
131			`CASR_outCASR [12]=CASR_varCASR [11]^CASR_varCASR [13];`
132			`CASR_outCASR [11]=CASR_varCASR [10]^CASR_varCASR [12];`
133			`CASR_outCASR [10]=CASR_varCASR [9]^CASR_varCASR [11];`
134			`CASR_outCASR [9]=CASR_varCASR [8]^CASR_varCASR [10];`
135			`CASR_outCASR [8]=CASR_varCASR [7]^CASR_varCASR [9];`
136			`CASR_outCASR [7]=CASR_varCASR [6]^CASR_varCASR [8];`
137			`CASR_outCASR [6]=CASR_varCASR [5]^CASR_varCASR [7];`
138			`CASR_outCASR [5]=CASR_varCASR [4]^CASR_varCASR [6];`
139			`CASR_outCASR [4]=CASR_varCASR [3]^CASR_varCASR [5];`
140			`CASR_outCASR [3]=CASR_varCASR [2]^CASR_varCASR [4];`
141			`CASR_outCASR [2]=CASR_varCASR [1]^CASR_varCASR [3];`
142			`CASR_outCASR [1]=CASR_varCASR [0]^CASR_varCASR [2];`
143			`CASR_outCASR [0]=CASR_varCASR [36]^CASR_varCASR [1];`
144
145			`CASR_reg = (CASR_outCASR );`
146
147			`end`
148
149
150			`end`
151
152
153			`end`
154			`//LFSR:`
155			`reg[42:0] LFSR_varLFSR;`
156			`reg outbitLFSR;`
157			`always @(posedge clk or negedge reset)`
158
159			`begin`
160
161
162			`if (!reset )`
163
164			`begin`
165
166			`LFSR_reg = (1);`
167
168			`end`
169
170			`else`
171
172			`begin`
173
174			`if (loadseed_i )`
175
176			`begin`
177
178	10	jcastillo	`LFSR_varLFSR [42:32]=0;`
179	7	jcastillo	`LFSR_varLFSR [31:0]=seed_i ;`
180			`LFSR_reg = (LFSR_varLFSR );`
181
182
183			`end`
184
185			`else`
186
187			`begin`
188
189			`LFSR_varLFSR =LFSR_reg ;`
190
191			`outbitLFSR =LFSR_varLFSR [42];`
192			`LFSR_varLFSR [42]=LFSR_varLFSR [41];`
193			`LFSR_varLFSR [41]=LFSR_varLFSR [40]^outbitLFSR ;`
194			`LFSR_varLFSR [40]=LFSR_varLFSR [39];`
195			`LFSR_varLFSR [39]=LFSR_varLFSR [38];`
196			`LFSR_varLFSR [38]=LFSR_varLFSR [37];`
197			`LFSR_varLFSR [37]=LFSR_varLFSR [36];`
198			`LFSR_varLFSR [36]=LFSR_varLFSR [35];`
199			`LFSR_varLFSR [35]=LFSR_varLFSR [34];`
200			`LFSR_varLFSR [34]=LFSR_varLFSR [33];`
201			`LFSR_varLFSR [33]=LFSR_varLFSR [32];`
202			`LFSR_varLFSR [32]=LFSR_varLFSR [31];`
203			`LFSR_varLFSR [31]=LFSR_varLFSR [30];`
204			`LFSR_varLFSR [30]=LFSR_varLFSR [29];`
205			`LFSR_varLFSR [29]=LFSR_varLFSR [28];`
206			`LFSR_varLFSR [28]=LFSR_varLFSR [27];`
207			`LFSR_varLFSR [27]=LFSR_varLFSR [26];`
208			`LFSR_varLFSR [26]=LFSR_varLFSR [25];`
209			`LFSR_varLFSR [25]=LFSR_varLFSR [24];`
210			`LFSR_varLFSR [24]=LFSR_varLFSR [23];`
211			`LFSR_varLFSR [23]=LFSR_varLFSR [22];`
212			`LFSR_varLFSR [22]=LFSR_varLFSR [21];`
213			`LFSR_varLFSR [21]=LFSR_varLFSR [20];`
214			`LFSR_varLFSR [20]=LFSR_varLFSR [19]^outbitLFSR ;`
215			`LFSR_varLFSR [19]=LFSR_varLFSR [18];`
216			`LFSR_varLFSR [18]=LFSR_varLFSR [17];`
217			`LFSR_varLFSR [17]=LFSR_varLFSR [16];`
218			`LFSR_varLFSR [16]=LFSR_varLFSR [15];`
219			`LFSR_varLFSR [15]=LFSR_varLFSR [14];`
220			`LFSR_varLFSR [14]=LFSR_varLFSR [13];`
221			`LFSR_varLFSR [13]=LFSR_varLFSR [12];`
222			`LFSR_varLFSR [12]=LFSR_varLFSR [11];`
223			`LFSR_varLFSR [11]=LFSR_varLFSR [10];`
224			`LFSR_varLFSR [10]=LFSR_varLFSR [9];`
225			`LFSR_varLFSR [9]=LFSR_varLFSR [8];`
226			`LFSR_varLFSR [8]=LFSR_varLFSR [7];`
227			`LFSR_varLFSR [7]=LFSR_varLFSR [6];`
228			`LFSR_varLFSR [6]=LFSR_varLFSR [5];`
229			`LFSR_varLFSR [5]=LFSR_varLFSR [4];`
230			`LFSR_varLFSR [4]=LFSR_varLFSR [3];`
231			`LFSR_varLFSR [3]=LFSR_varLFSR [2];`
232			`LFSR_varLFSR [2]=LFSR_varLFSR [1];`
233			`LFSR_varLFSR [1]=LFSR_varLFSR [0]^outbitLFSR ;`
234			`LFSR_varLFSR [0]=LFSR_varLFSR [42];`
235
236			`LFSR_reg = (LFSR_varLFSR );`
237
238			`end`
239
240
241			`end`
242
243
244			`end`
245			`//combinate:`
246			`always @(posedge clk or negedge reset)`
247
248			`begin`
249
250			`if (!reset )`
251
252			`begin`
253
254			`number_o = (0);`
255
256			`end`
257
258			`else`
259
260			`begin`
261
262			`number_o = (LFSR_reg [31:0]^CASR_reg[31:0]);`
263
264			`end`
265
266
267			`end`
268
269			`endmodule`