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//////////////////////////////////////////////////////////////////////

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////  Random testbench declation                                  ////

////                                                              ////

////  This file is part of the SystemC AES                        ////

////                                                              ////

////  Description:                                                ////

////  Declare ramdom testbench class and data                     ////

////                                                              ////

////  To Do:                                                      ////

////   - done                                                     ////

////                                                              ////

////  Author(s):                                                  ////

////      - Javier Castillo, jcastilo@opencores.org               ////

////                                                              ////

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////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.2  2004/08/30 14:47:38  jcastillo

// Code formated

//

// Revision 1.1.1.1  2004/07/05 09:46:22  jcastillo

// First import

//

#include "transactor.h"

#include "scv.h"

//Random number generator

class random_generator: virtual public scv_constraint_base

{

public:

        scv_smart_ptr<sc_biguint<128> > aes_key;

        scv_smart_ptr<sc_biguint<128> > aes_data;

        scv_smart_ptr<bool> decrypt;

        SCV_CONSTRAINT_CTOR(random_generator) {}

};

class test: public sc_module

{

public:

        sc_port<rw_task_if> transactor;

        void tb();

        SC_CTOR(test)

        {

                SC_THREAD(tb);

        }

};