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[/] [systemcaes/] [trunk/] [rtl/] [verilog/] [aes128lowarea/] [wb_aescontroller.v] - Blame information for rev 28

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Wishbone Interface for AES128 Coprocessor                   ////
////                                                              ////
////  This file is part of the SystemC AES                        ////
////                                                              ////
////  To Do:                                                      ////
////   - done                                                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, jcastilo@opencores.org               ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
`include "timescale.v"
 
module wb_aes_controller(clk,reset,wb_stb_i,wb_dat_o,wb_dat_i,wb_ack_o,
                         wb_adr_i,wb_we_i,wb_cyc_i,wb_sel_i,
                         load_o,decrypt_o,ready_i,data_o,key_o,data_i);
 
input         clk;
input         reset;
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [31:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
 
output         load_o;
output         decrypt_o;
output [127:0] data_o;
output [127:0] key_o;
input  [127:0] data_i;
input          ready_i;
 
reg  [31:0]  wb_dat_o;
reg          wb_ack_o;
 
reg  [127:0]  data_o;
reg  [127:0]  key_o;
wire         load_o;
wire         decrypt_o;
 
reg  [31:0]  control_reg;
reg  [127:0]  cypher_data_reg;
 
assign load_o = control_reg[0];
assign decrypt_o = control_reg[2];
 
always @(posedge clk or posedge reset)
begin
     if(reset==1)
     begin
       wb_ack_o<=#1 0;
       wb_dat_o<=#1 0;
       control_reg <= #1 32'h0;
       cypher_data_reg <= #1 127'h0;
       key_o <= #1 127'h0;
       data_o <= #1 127'h0;
     end
     else
     begin
       if(ready_i)
       begin
        control_reg[1] <= #1 1'b1;
        cypher_data_reg <= #1 data_i;
       end
 
       if(wb_stb_i && wb_cyc_i && wb_we_i && ~wb_ack_o)
       begin
         wb_ack_o<=#1 1;
         case(wb_adr_i[7:0])
             8'h0:
             begin
                 //Writing control register
                 control_reg<= #1 wb_dat_i;
             end
             8'h4:
              begin
                 data_o[127:96]<= #1 wb_dat_i;
             end
             8'h8:
             begin
                 data_o[95:64]<= #1 wb_dat_i;
             end
                         8'hC:
              begin
                 data_o[63:32]<= #1 wb_dat_i;
             end
             8'h10:
             begin
                 data_o[31:0]<= #1 wb_dat_i;
             end
             8'h14:
             begin
                 key_o[127:96]<= #1 wb_dat_i;
             end
             8'h18:
             begin
                 key_o[95:64]<= #1 wb_dat_i;
             end
             8'h1C:
             begin
                 key_o[63:32]<= #1 wb_dat_i;
             end
             8'h20:
             begin
                 key_o[31:0]<= #1 wb_dat_i;
             end
         endcase
       end
       else if(wb_stb_i && wb_cyc_i && ~wb_we_i && ~wb_ack_o)
       begin
           wb_ack_o<=#1 1;
           case(wb_adr_i[7:0])
             8'h0:
             begin
                 wb_dat_o<= #1 control_reg;
                 control_reg[1]<=1'b0;
             end
             8'h24:
             begin
                 wb_dat_o<= #1 cypher_data_reg[127:96];
             end
             8'h28:
             begin
                 wb_dat_o<= #1 cypher_data_reg[95:64];
             end
                         8'h2C:
             begin
                 wb_dat_o<= #1 cypher_data_reg[63:32];
             end
             8'h30:
             begin
                 wb_dat_o<= #1 cypher_data_reg[31:0];
             end
           endcase
       end
       else
       begin
           wb_ack_o<=#1 0;
           control_reg[0]<= #1 1'b0;
       end
 
     end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	27	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Wishbone Interface for AES128 Coprocessor ////`
4			`//// ////`
5			`//// This file is part of the SystemC AES ////`
6			`//// ////`
7			`//// To Do: ////`
8			`//// - done ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// - Javier Castillo, jcastilo@opencores.org ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39			`//`
40			`// CVS Revision History`
41			`//`
42			`// $Log: not supported by cvs2svn $`
43			`//`
44			`include "timescale.v"
45
46			`module wb_aes_controller(clk,reset,wb_stb_i,wb_dat_o,wb_dat_i,wb_ack_o,`
47			`wb_adr_i,wb_we_i,wb_cyc_i,wb_sel_i,`
48			`load_o,decrypt_o,ready_i,data_o,key_o,data_i);`
49
50			`input clk;`
51			`input reset;`
52			`input wb_stb_i;`
53			`output [31:0] wb_dat_o;`
54			`input [31:0] wb_dat_i;`
55			`output wb_ack_o;`
56			`input [31:0] wb_adr_i;`
57			`input wb_we_i;`
58			`input wb_cyc_i;`
59			`input [3:0] wb_sel_i;`
60
61			`output load_o;`
62			`output decrypt_o;`
63			`output [127:0] data_o;`
64			`output [127:0] key_o;`
65			`input [127:0] data_i;`
66			`input ready_i;`
67
68			`reg [31:0] wb_dat_o;`
69			`reg wb_ack_o;`
70
71			`reg [127:0] data_o;`
72			`reg [127:0] key_o;`
73			`wire load_o;`
74			`wire decrypt_o;`
75
76			`reg [31:0] control_reg;`
77			`reg [127:0] cypher_data_reg;`
78
79			`assign load_o = control_reg[0];`
80			`assign decrypt_o = control_reg[2];`
81
82			`always @(posedge clk or posedge reset)`
83			`begin`
84			`if(reset==1)`
85			`begin`
86			`wb_ack_o<=#1 0;`
87			`wb_dat_o<=#1 0;`
88			`control_reg <= #1 32'h0;`
89			`cypher_data_reg <= #1 127'h0;`
90			`key_o <= #1 127'h0;`
91			`data_o <= #1 127'h0;`
92			`end`
93			`else`
94			`begin`
95			`if(ready_i)`
96			`begin`
97			`control_reg[1] <= #1 1'b1;`
98			`cypher_data_reg <= #1 data_i;`
99			`end`
100
101			`if(wb_stb_i && wb_cyc_i && wb_we_i && ~wb_ack_o)`
102			`begin`
103			`wb_ack_o<=#1 1;`
104			`case(wb_adr_i[7:0])`
105			`8'h0:`
106			`begin`
107			`//Writing control register`
108			`control_reg<= #1 wb_dat_i;`
109			`end`
110			`8'h4:`
111			`begin`
112			`data_o[127:96]<= #1 wb_dat_i;`
113			`end`
114			`8'h8:`
115			`begin`
116			`data_o[95:64]<= #1 wb_dat_i;`
117			`end`
118			`8'hC:`
119			`begin`
120			`data_o[63:32]<= #1 wb_dat_i;`
121			`end`
122			`8'h10:`
123			`begin`
124			`data_o[31:0]<= #1 wb_dat_i;`
125			`end`
126			`8'h14:`
127			`begin`
128			`key_o[127:96]<= #1 wb_dat_i;`
129			`end`
130			`8'h18:`
131			`begin`
132			`key_o[95:64]<= #1 wb_dat_i;`
133			`end`
134			`8'h1C:`
135			`begin`
136			`key_o[63:32]<= #1 wb_dat_i;`
137			`end`
138			`8'h20:`
139			`begin`
140			`key_o[31:0]<= #1 wb_dat_i;`
141			`end`
142			`endcase`
143			`end`
144			`else if(wb_stb_i && wb_cyc_i && ~wb_we_i && ~wb_ack_o)`
145			`begin`
146			`wb_ack_o<=#1 1;`
147			`case(wb_adr_i[7:0])`
148			`8'h0:`
149			`begin`
150			`wb_dat_o<= #1 control_reg;`
151			`control_reg[1]<=1'b0;`
152			`end`
153			`8'h24:`
154			`begin`
155			`wb_dat_o<= #1 cypher_data_reg[127:96];`
156			`end`
157			`8'h28:`
158			`begin`
159			`wb_dat_o<= #1 cypher_data_reg[95:64];`
160			`end`
161			`8'h2C:`
162			`begin`
163			`wb_dat_o<= #1 cypher_data_reg[63:32];`
164			`end`
165			`8'h30:`
166			`begin`
167			`wb_dat_o<= #1 cypher_data_reg[31:0];`
168			`end`
169			`endcase`
170			`end`
171			`else`
172			`begin`
173			`wb_ack_o<=#1 0;`
174			`control_reg[0]<= #1 1'b0;`
175			`end`
176
177			`end`
178			`end`
179
180
181			`endmodule`
182

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[/] [systemcaes/] [trunk/] [rtl/] [verilog/] [aes128lowarea/] [wb_aescontroller.v] - Blame information for rev 28