URL https://opencores.org/ocsvn/systemverilog-uart16550/systemverilog-uart16550/trunk

Subversion Repositories systemverilog-uart16550

[/] [systemverilog-uart16550/] [trunk/] [bench/] [uart_top_package.sv] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


/* *****************************************************************************
   * title:         uart_16550_rll module                                      *
   * description:   RS232 Protocol 16550D uart (mostly supported)              *
   * languages:     systemVerilog                                              *
   *                                                                           *
   * Copyright (C) 2010 miyagi.hiroshi                                         *
   *                                                                           *
   * This library is free software; you can redistribute it and/or             *
   * modify it under the terms of the GNU Lesser General Public                *
   * License as published by the Free Software Foundation; either              *
   * version 2.1 of the License, or (at your option) any later version.        *
   *                                                                           *
   * This library is distributed in the hope that it will be useful,           *
   * but WITHOUT ANY WARRANTY; without even the implied warranty of            *
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU         *
   * Lesser General Public License for more details.                           *
   *                                                                           *
   * You should have received a copy of the GNU Lesser General Public          *
   * License along with this library; if not, write to the Free Software       *
   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111*1307  USA *
   *                                                                           *
   *         ***  GNU LESSER GENERAL PUBLIC LICENSE  ***                       *
   *           from http://www.gnu.org/licenses/lgpl.txt                       *
   *****************************************************************************
   *                            redleaflogic,ltd                               *
   *                    miyagi.hiroshi@redleaflogic.biz                        *
   *          $Id: uart_top_package.sv 108 2010-03-30 02:56:26Z hiroshi $         *
   ***************************************************************************** */
 
package uart_top_package ;
`ifdef SYN
 /* empty */
`else
   timeunit      1ps ;
   timeprecision 1ps ;
`endif
 
parameter  STEP = 50000 ;
 
endpackage : uart_top_package

Line No.	Rev	Author	Line
1	2	hiroshi	`/* *****************************************************************************`
2			`* title: uart_16550_rll module *`
3			`* description: RS232 Protocol 16550D uart (mostly supported) *`
4			`* languages: systemVerilog *`
5			`* *`
6			`* Copyright (C) 2010 miyagi.hiroshi *`
7			`* *`
8			`* This library is free software; you can redistribute it and/or *`
9			`* modify it under the terms of the GNU Lesser General Public *`
10			`* License as published by the Free Software Foundation; either *`
11			`* version 2.1 of the License, or (at your option) any later version. *`
12			`* *`
13			`* This library is distributed in the hope that it will be useful, *`
14			`* but WITHOUT ANY WARRANTY; without even the implied warranty of *`
15			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *`
16			`* Lesser General Public License for more details. *`
17			`* *`
18			`* You should have received a copy of the GNU Lesser General Public *`
19			`* License along with this library; if not, write to the Free Software *`
20			`* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 021111307 USA `
21			`* *`
22			`* * GNU LESSER GENERAL PUBLIC LICENSE * *`
23			`* from http://www.gnu.org/licenses/lgpl.txt *`
24			`*****************************************************************************`
25			`* redleaflogic,ltd *`
26			`* miyagi.hiroshi@redleaflogic.biz *`
27			`* $Id: uart_top_package.sv 108 2010-03-30 02:56:26Z hiroshi $ *`
28			`***************************************************************************** */`
29
30			`package uart_top_package ;`
31			`ifdef SYN
32			`/* empty */`
33			`else
34			`timeunit 1ps ;`
35			`timeprecision 1ps ;`
36			`endif
37
38			`parameter STEP = 50000 ;`
39
40			`endpackage : uart_top_package`

Browse

Tools

Subversion Repositories systemverilog-uart16550

[/] [systemverilog-uart16550/] [trunk/] [bench/] [uart_top_package.sv] - Blame information for rev 6