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[/] [systemverilog-uart16550/] [trunk/] [rtl/] [uart_receiver.sv] - Blame information for rev 8

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1 2 hiroshi
/* *****************************************************************************
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   * title:         uart_16550_rll module                                      *
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   * description:   RS232 Protocol 16550D uart (mostly supported)              *
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   * languages:     systemVerilog                                              *
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   *                                                                           *
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   * Copyright (C) 2010 miyagi.hiroshi                                         *
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   *                                                                           *
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   * This library is free software; you can redistribute it and/or             *
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   * modify it under the terms of the GNU Lesser General Public                *
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   * License as published by the Free Software Foundation; either              *
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   * version 2.1 of the License, or (at your option) any later version.        *
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   *                                                                           *
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   * This library is distributed in the hope that it will be useful,           *
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   * but WITHOUT ANY WARRANTY; without even the implied warranty of            *
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   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU         *
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   * Lesser General Public License for more details.                           *
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   *                                                                           *
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   * You should have received a copy of the GNU Lesser General Public          *
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   * License along with this library; if not, write to the Free Software       *
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   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111*1307  USA *
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   *                                                                           *
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   *         ***  GNU LESSER GENERAL PUBLIC LICENSE  ***                       *
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   *           from http://www.gnu.org/licenses/lgpl.txt                       *
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   *****************************************************************************
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   *                            redleaflogic,ltd                               *
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   *                    miyagi.hiroshi@redleaflogic.biz                        *
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   *          $Id: uart_receiver.sv 108 2010-03-30 02:56:26Z hiroshi $         *
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   ***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit      1ps ;
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timeprecision 1ps ;
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`endif
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import uart_package:: * ;
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module uart_receiver(
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                     input wire     clk_i,
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                     input wire     nrst_i,
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                     input wire     rxd_clean,
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                     input wire     rec_clk_en,
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                     input wire     rec_sample_pulse,
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                     input wire     leading_edge,
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                     input wire     timeout_signal,
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                     fifo_bus       fifo_push,
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                     input  u_reg_t u_reg,
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                     output codec_state_t next_state,
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                     output  logic  rec_buf_empty,
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                     output  logic  overrun
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                     ) ;
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   //   codec_state_t     next_state ;
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   u_codec_t         rec_codec ;
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   always @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0)
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        rec_codec.line <= #1 1'b1 ;
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      else
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        rec_codec.line <= #1 rxd_clean ;
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   end
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   // --- fifo push --
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   assign fifo_push.push_dat =  {rec_codec.parity_err,    // bit[10]
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                                 rec_codec.framing_err,   //     9
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                                 rec_codec.break_err,     //     8
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                                 rec_codec.data_r}  ;     //     [7:0]
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   logic push_dly ;
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   always @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0)
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        push_dly <= #1 1'b0 ;
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      else
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        push_dly <= #1 next_state == STOP && rec_sample_pulse == 1'b1 ;
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   end
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   assign fifo_push.push = push_dly == 1'b1 ;
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   // -- trasmitter state logic --
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   uart_codec_state rec_state(.u_reg(u_reg),
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                              .codec(rec_codec),
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                              .receiver_mode(1'b1),
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                              .timeout_signal(timeout_signal),
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                              .next_state(next_state)) ;
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   // -- state register --
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   always_ff @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0)
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        rec_codec.state <= #1 IDLE ;
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      else if(rec_clk_en == 1'b1 || leading_edge == 1'b1)
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        rec_codec.state <= #1 next_state ;
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      else
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        rec_codec.state <= #1 rec_codec.state ;
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   end
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   // -- line input --
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   always_ff @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0) begin
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         rec_codec.data_r <= #1 8'h00 ;
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         rec_codec.framing_err <= #1 1'b0 ;
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         rec_codec.parity_err  <= #1 1'b0 ;
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         rec_codec.break_err   <= #1 1'b0 ;
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         overrun <= #1 1'b0 ;
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      end
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      else begin
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         if(rec_sample_pulse == 1'b1)
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           case (next_state)
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             IDLE  : /* empty */ ;
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             START : begin
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                overrun   <= #1 1'b0 ;
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                rec_codec.framing_err <= #1 1'b0 ;
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                rec_codec.parity_err  <= #1 1'b0 ;
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                rec_codec.break_err   <= #1 1'b0 ;
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             end
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             SEL_0 : rec_codec.data_r[0] <= #1 rec_codec.line ;
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             SEL_1 : rec_codec.data_r[1] <= #1 rec_codec.line ;
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             SEL_2 : rec_codec.data_r[2] <= #1 rec_codec.line ;
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             SEL_3 : rec_codec.data_r[3] <= #1 rec_codec.line ;
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             SEL_4 : rec_codec.data_r[4] <= #1 rec_codec.line ;
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             SEL_5 : rec_codec.data_r[5] <= #1 rec_codec.line ;
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             SEL_6 : rec_codec.data_r[6] <= #1 rec_codec.line ;
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             DATA_END : begin
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                if(u_reg.line_control_reg.char_length == CHAR_7_BIT) begin
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                   rec_codec.data_r[6] <= #1 rec_codec.line ;
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                   rec_codec.data_r[7] <= #1 1'b0 ;
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                end
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                else begin
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                   rec_codec.data_r[7] <= #1 rec_codec.line ;
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                end
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                overrun <= #1 fifo_push.full ;
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             end
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             PARITY : begin
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                if(u_reg.line_control_reg.even_parity == 1'b1)
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                  rec_codec.parity_err <= #1 (^rec_codec.data_r) ^ rec_codec.line ;
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                else
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                  rec_codec.parity_err <= #1 ~(^rec_codec.data_r) ^ rec_codec.line ;
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             end
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             STOP  : begin
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                rec_codec.framing_err <= #1 rec_codec.line == 1'b0 &&
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                                         rec_codec.data_r[7:0] != 8'h00 ;
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                rec_codec.break_err <= #1 rec_codec.data_r[7:0] == 8'h00 &&
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                                       rec_codec.line == 1'b0 &&
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                                       rec_codec.parity_err == 1'b0 ;
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             end
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             default : /* empty */ ;
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           endcase // case (state)
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      end // if (sample_en == 1'b1)
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   end // always_ff @ (posedge clk, negedge nrst)
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   always_ff @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0)
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        rec_buf_empty <= 1'b0 ;
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      else if(next_state == IDLE || next_state == STOP)
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        rec_buf_empty <= #1 1'b1 ;
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      else
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        rec_buf_empty <= #1 1'b0 ;
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   end
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   always_ff @(posedge clk_i, negedge nrst_i) begin
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      if(nrst_i == 1'b0)
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        rec_codec.start <= #1 1'b0 ;
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      else if(rec_codec.state == START)
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        rec_codec.start <= #1 1'b0 ;
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      else if(leading_edge == 1'b1)
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        rec_codec.start <= #1 1'b1 ;
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      else
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        rec_codec.start <= #1 rec_codec.start ;
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   end
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endmodule
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/// END OF FILE ///

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