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        ;; *******************************************************************
        ;; $Id: test.asm,v 1.1 2006-05-23 01:11:13 arniml Exp $
        ;;
        ;; Checks the INIL instruction.
        ;;
 
        ;; the cpu type is defined on asl's command line
 
        org     0x00
        clra
 
        ;; check reset level of latches
        inil
        x       0
        skmbz   3
        jmp     fail
        skmbz   0
        jmp     fail
 
 
        ;; set IN to 0xf and recheck levels
        ogi     0xf
        nop
        nop
        inil
        x       0
        skmbz   3
        jmp     fail
        skmbz   0
        jmp     fail
 
 
        ;; set IN0 to 0 and check that IL0 triggered
        ogi     0xe
        nop
        inil
        x       0
        skmbz   3
        jmp     fail
        skmbz   0
        jp      +
        jmp     fail
+
 
 
        ;; set IN3 to 0 and check that IL1 triggered
        ogi     0x6
        nop
        inil
        x       0
        skmbz   3
        jp      +
        jmp     fail
+       skmbz   0
        jmp     fail
 
 
        jmp     page_1
        org     0x040
page_1:
        ;; reload IN3 to trigger both IL latches
        ogi     0x9
        ogi     0x0
        nop
        inil
        x       0
        skmbz   3
        jp      +
        jmp     fail
+       skmbz   0
        jp      +
        jmp     fail
+
 
 
        ;; check that INIL prevents setting of IL latches
        ;; when both events occur at the same cycle
        ogi     0x9
        ogi     0x0
        inil
        x       0
        skmbz   3
        jmp     fail
        skmbz   0
        jmp     fail
 
 
        jmp     pass
 
 
        org     0x100
        include "pass_fail.asm"

Line No.	Rev	Author	Line
1	51	arniml	`;; *******************************************************************`
2			`;; $Id: test.asm,v 1.1 2006-05-23 01:11:13 arniml Exp $`
3			`;;`
4			`;; Checks the INIL instruction.`
5			`;;`
6
7			`;; the cpu type is defined on asl's command line`
8
9			`org 0x00`
10			`clra`
11
12			`;; check reset level of latches`
13			`inil`
14			`x 0`
15			`skmbz 3`
16			`jmp fail`
17			`skmbz 0`
18			`jmp fail`
19
20
21			`;; set IN to 0xf and recheck levels`
22			`ogi 0xf`
23			`nop`
24			`nop`
25			`inil`
26			`x 0`
27			`skmbz 3`
28			`jmp fail`
29			`skmbz 0`
30			`jmp fail`
31
32
33			`;; set IN0 to 0 and check that IL0 triggered`
34			`ogi 0xe`
35			`nop`
36			`inil`
37			`x 0`
38			`skmbz 3`
39			`jmp fail`
40			`skmbz 0`
41			`jp +`
42			`jmp fail`
43			`+`
44
45
46			`;; set IN3 to 0 and check that IL1 triggered`
47			`ogi 0x6`
48			`nop`
49			`inil`
50			`x 0`
51			`skmbz 3`
52			`jp +`
53			`jmp fail`
54			`+ skmbz 0`
55			`jmp fail`
56
57
58			`jmp page_1`
59			`org 0x040`
60			`page_1:`
61			`;; reload IN3 to trigger both IL latches`
62			`ogi 0x9`
63			`ogi 0x0`
64			`nop`
65			`inil`
66			`x 0`
67			`skmbz 3`
68			`jp +`
69			`jmp fail`
70			`+ skmbz 0`
71			`jp +`
72			`jmp fail`
73			`+`
74
75
76			`;; check that INIL prevents setting of IL latches`
77			`;; when both events occur at the same cycle`
78			`ogi 0x9`
79			`ogi 0x0`
80			`inil`
81			`x 0`
82			`skmbz 3`
83			`jmp fail`
84			`skmbz 0`
85			`jmp fail`
86
87
88			`jmp pass`
89
90
91			`org 0x100`
92			`include "pass_fail.asm"`

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[/] [t400/] [tags/] [rel_1_1/] [sw/] [verif/] [black_box/] [inil/] [test.asm] - Blame information for rev 51