OpenCores
URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [rtl/] [vhdl/] [system/] [t410_notri.vhd] - Blame information for rev 176

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 arniml
-------------------------------------------------------------------------------
2
--
3
-- T410/411 controller toplevel without tri-states.
4
--
5 173 arniml
-- $Id: t410_notri.vhd,v 1.4 2008-08-23 11:19:20 arniml Exp $
6
-- $Name: not supported by cvs2svn $
7 2 arniml
--
8
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
9
--
10
-- All rights reserved
11
--
12
-- Redistribution and use in source and synthezised forms, with or without
13
-- modification, are permitted provided that the following conditions are met:
14
--
15
-- Redistributions of source code must retain the above copyright notice,
16
-- this list of conditions and the following disclaimer.
17
--
18
-- Redistributions in synthesized form must reproduce the above copyright
19
-- notice, this list of conditions and the following disclaimer in the
20
-- documentation and/or other materials provided with the distribution.
21
--
22
-- Neither the name of the author nor the names of other contributors may
23
-- be used to endorse or promote products derived from this software without
24
-- specific prior written permission.
25
--
26
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
30
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36
-- POSSIBILITY OF SUCH DAMAGE.
37
--
38
-- Please report bugs to the author, but before you do so, please
39
-- make sure that this is not a derivative work and that
40
-- you have the latest version of this file.
41
--
42
-- The latest version of this file can be found at:
43
--      http://www.opencores.org/cvsweb.shtml/t400/
44
--
45
-------------------------------------------------------------------------------
46
 
47
library ieee;
48
use ieee.std_logic_1164.all;
49
 
50
use work.t400_opt_pack.all;
51
 
52
entity t410_notri is
53
 
54
  generic (
55
    opt_ck_div_g         : integer := t400_opt_ck_div_16_c;
56
    opt_cko_g            : integer := t400_opt_cko_crystal_c;
57
    opt_l_out_type_7_g   : integer := t400_opt_out_type_std_c;
58
    opt_l_out_type_6_g   : integer := t400_opt_out_type_std_c;
59
    opt_l_out_type_5_g   : integer := t400_opt_out_type_std_c;
60
    opt_l_out_type_4_g   : integer := t400_opt_out_type_std_c;
61
    opt_l_out_type_3_g   : integer := t400_opt_out_type_std_c;
62
    opt_l_out_type_2_g   : integer := t400_opt_out_type_std_c;
63
    opt_l_out_type_1_g   : integer := t400_opt_out_type_std_c;
64
    opt_l_out_type_0_g   : integer := t400_opt_out_type_std_c;
65
    opt_d_out_type_3_g   : integer := t400_opt_out_type_std_c;
66
    opt_d_out_type_2_g   : integer := t400_opt_out_type_std_c;
67
    opt_d_out_type_1_g   : integer := t400_opt_out_type_std_c;
68
    opt_d_out_type_0_g   : integer := t400_opt_out_type_std_c;
69
    opt_g_out_type_3_g   : integer := t400_opt_out_type_std_c;
70
    opt_g_out_type_2_g   : integer := t400_opt_out_type_std_c;
71
    opt_g_out_type_1_g   : integer := t400_opt_out_type_std_c;
72
    opt_g_out_type_0_g   : integer := t400_opt_out_type_std_c;
73
    opt_so_output_type_g : integer := t400_opt_out_type_std_c;
74
    opt_sk_output_type_g : integer := t400_opt_out_type_std_c
75
  );
76
  port (
77
    ck_i      : in  std_logic;
78
    ck_en_i   : in  std_logic;
79
    reset_n_i : in  std_logic;
80
    cko_i     : in  std_logic;
81
    io_l_i    : in  std_logic_vector(7 downto 0);
82
    io_l_o    : out std_logic_vector(7 downto 0);
83
    io_l_en_o : out std_logic_vector(7 downto 0);
84
    io_d_o    : out std_logic_vector(3 downto 0);
85
    io_d_en_o : out std_logic_vector(3 downto 0);
86
    io_g_i    : in  std_logic_vector(3 downto 0);
87
    io_g_o    : out std_logic_vector(3 downto 0);
88
    io_g_en_o : out std_logic_vector(3 downto 0);
89
    si_i      : in  std_logic;
90
    so_o      : out std_logic;
91
    so_en_o   : out std_logic;
92
    sk_o      : out std_logic;
93
    sk_en_o   : out std_logic
94
  );
95
 
96
end t410_notri;
97
 
98
 
99
use work.t400_core_comp_pack.t400_core;
100
use work.t400_tech_comp_pack.t400_por;
101 108 arniml
use work.t400_tech_comp_pack.generic_ram_ena;
102 2 arniml
 
103
architecture struct of t410_notri is
104
 
105
  component t410_rom
106
    port (
107
      ck_i   : in  std_logic;
108
      addr_i : in  std_logic_vector(8 downto 0);
109
      data_o : out std_logic_vector(7 downto 0)
110
    );
111
  end component;
112
 
113
  signal por_n_s             : std_logic;
114
 
115
  signal pm_addr_s           : std_logic_vector(9 downto 0);
116
  signal pm_data_s           : std_logic_vector(7 downto 0);
117
 
118
  signal dm_addr_s           : std_logic_vector(5 downto 0);
119
  signal dm_we_s             : std_logic;
120
  signal dm_data_to_core_s,
121
         dm_data_from_core_s : std_logic_vector(3 downto 0);
122
 
123
  signal gnd4_s              : std_logic_vector(3 downto 0);
124
 
125
begin
126
 
127
  gnd4_s <= (others => '0');
128
 
129
  -----------------------------------------------------------------------------
130
  -- T400 core
131
  -----------------------------------------------------------------------------
132
  core_b : t400_core
133
    generic map (
134
      opt_type_g           => t400_opt_type_410_c,
135 13 arniml
      opt_ck_div_g         => opt_ck_div_g,
136 2 arniml
      opt_cko_g            => opt_cko_g,
137
      opt_l_out_type_7_g   => opt_l_out_type_7_g,
138
      opt_l_out_type_6_g   => opt_l_out_type_6_g,
139
      opt_l_out_type_5_g   => opt_l_out_type_5_g,
140
      opt_l_out_type_4_g   => opt_l_out_type_4_g,
141
      opt_l_out_type_3_g   => opt_l_out_type_3_g,
142
      opt_l_out_type_2_g   => opt_l_out_type_2_g,
143
      opt_l_out_type_1_g   => opt_l_out_type_1_g,
144
      opt_l_out_type_0_g   => opt_l_out_type_0_g,
145
      opt_microbus_g       => t400_opt_no_microbus_c,
146
      opt_d_out_type_3_g   => opt_d_out_type_3_g,
147
      opt_d_out_type_2_g   => opt_d_out_type_2_g,
148
      opt_d_out_type_1_g   => opt_d_out_type_1_g,
149
      opt_d_out_type_0_g   => opt_d_out_type_0_g,
150
      opt_g_out_type_3_g   => opt_g_out_type_3_g,
151
      opt_g_out_type_2_g   => opt_g_out_type_2_g,
152
      opt_g_out_type_1_g   => opt_g_out_type_1_g,
153
      opt_g_out_type_0_g   => opt_g_out_type_0_g,
154
      opt_so_output_type_g => opt_so_output_type_g,
155
      opt_sk_output_type_g => opt_sk_output_type_g
156
    )
157
    port map (
158
      ck_i      => ck_i,
159
      ck_en_i   => ck_en_i,
160
      por_n_i   => por_n_s,
161
      reset_n_i => reset_n_i,
162
      cko_i     => cko_i,
163
      pm_addr_o => pm_addr_s,
164
      pm_data_i => pm_data_s,
165
      dm_addr_o => dm_addr_s,
166
      dm_we_o   => dm_we_s,
167
      dm_data_o => dm_data_from_core_s,
168
      dm_data_i => dm_data_to_core_s,
169
      io_l_i    => io_l_i,
170
      io_l_o    => io_l_o,
171
      io_l_en_o => io_l_en_o,
172
      io_d_o    => io_d_o,
173
      io_d_en_o => io_d_en_o,
174
      io_g_i    => io_g_i,
175
      io_g_o    => io_g_o,
176
      io_g_en_o => io_g_en_o,
177
      io_in_i   => gnd4_s,
178
      si_i      => si_i,
179
      so_o      => so_o,
180
      so_en_o   => so_en_o,
181
      sk_o      => sk_o,
182
      sk_en_o   => sk_en_o
183
    );
184
 
185
 
186
  -----------------------------------------------------------------------------
187
  -- Program memory
188
  -----------------------------------------------------------------------------
189
  pmem_b : t410_rom
190
    port map (
191
      ck_i   => ck_i,
192
      addr_i => pm_addr_s(8 downto 0),
193
      data_o => pm_data_s
194
    );
195
 
196
 
197
  -----------------------------------------------------------------------------
198
  -- Data memory
199
  -----------------------------------------------------------------------------
200 108 arniml
  dmem_b : generic_ram_ena
201 2 arniml
    generic map (
202
      addr_width_g => 5,
203
      data_width_g => 4
204
    )
205
    port map (
206
      clk_i => ck_i,
207
      a_i   => dm_addr_s(4 downto 0),
208
      we_i  => dm_we_s,
209 108 arniml
      ena_i => ck_en_i,
210 2 arniml
      d_i   => dm_data_from_core_s,
211
      d_o   => dm_data_to_core_s
212
    );
213
 
214
 
215
  -----------------------------------------------------------------------------
216
  -- Power-on reset circuit
217
  -----------------------------------------------------------------------------
218
  por_b : t400_por
219
    generic map (
220
      delay_g     => 4,
221
      cnt_width_g => 2
222
    )
223
    port map (
224
      clk_i   => ck_i,
225
      por_n_o => por_n_s
226
    );
227
 
228
end struct;
229
 
230
 
231
-------------------------------------------------------------------------------
232
-- File History:
233
--
234
-- $Log: not supported by cvs2svn $
235 173 arniml
-- Revision 1.3  2006/06/05 20:03:11  arniml
236
-- include generic_ram_ena
237
--
238 108 arniml
-- Revision 1.2  2006/05/08 02:36:38  arniml
239
-- hand-down clock divider option
240
--
241 13 arniml
-- Revision 1.1.1.1  2006/05/06 01:56:45  arniml
242
-- import from local CVS repository, LOC_CVS_0_1
243
--
244 2 arniml
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.