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arniml |
-------------------------------------------------------------------------------
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--
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-- T400 Microcontroller Core
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--
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-- $Id: t400_core.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t400/
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--
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-- Limitations :
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-- =============
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--
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-- Compared to the original COP400 architecture, the following limitations
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-- apply:
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--
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-- * Features of the COP42x devices are either not yet implemented or
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-- not verified.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t400_opt_pack.all;
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entity t400_core is
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generic (
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opt_type_g : integer := t400_opt_type_420_c;
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opt_ck_div_g : integer := t400_opt_ck_div_16_c;
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opt_cko_g : integer := t400_opt_cko_crystal_c;
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opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
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opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
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opt_microbus_g : integer := t400_opt_no_microbus_c;
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opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
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opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
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opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
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opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
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opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
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opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
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opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
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opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
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opt_so_output_type_g : integer := t400_opt_out_type_std_c;
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opt_sk_output_type_g : integer := t400_opt_out_type_std_c
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);
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port (
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ck_i : in std_logic;
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ck_en_i : in std_logic;
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por_n_i : in std_logic;
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reset_n_i : in std_logic;
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cko_i : in std_logic;
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pm_addr_o : out std_logic_vector(9 downto 0);
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pm_data_i : in std_logic_vector(7 downto 0);
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dm_addr_o : out std_logic_vector(5 downto 0);
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dm_we_o : out std_logic;
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dm_data_o : out std_logic_vector(3 downto 0);
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dm_data_i : in std_logic_vector(3 downto 0);
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io_l_i : in std_logic_vector(7 downto 0);
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io_l_o : out std_logic_vector(7 downto 0);
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io_l_en_o : out std_logic_vector(7 downto 0);
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io_d_o : out std_logic_vector(3 downto 0);
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io_d_en_o : out std_logic_vector(3 downto 0);
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io_g_i : in std_logic_vector(3 downto 0);
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io_g_o : out std_logic_vector(3 downto 0);
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io_g_en_o : out std_logic_vector(3 downto 0);
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io_in_i : in std_logic_vector(3 downto 0);
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si_i : in std_logic;
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so_o : out std_logic;
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so_en_o : out std_logic;
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sk_o : out std_logic;
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sk_en_o : out std_logic
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);
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end t400_core;
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use work.t400_pack.all;
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use work.t400_comp_pack.all;
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architecture struct of t400_core is
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signal ck_en_s : boolean;
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signal por_s : boolean;
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signal res_s : boolean;
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signal phi1_s : std_logic;
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signal out_en_s : boolean;
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signal in_en_s : boolean;
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signal icyc_en_s : boolean;
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signal pm_addr_s : pc_t;
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signal a_s : dw_t;
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signal dec_data_s : dec_data_t;
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signal pc_to_stack_s,
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pc_from_stack_s : pc_t;
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signal q_s : byte_t;
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signal b_s : b_t;
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signal c_s,
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carry_s : std_logic;
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signal sio_s : dw_t;
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signal pc_op_s : pc_op_t;
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signal stack_op_s : stack_op_t;
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signal dmem_op_s : dmem_op_t;
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signal b_op_s : b_op_t;
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signal skip_op_s : skip_op_t;
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signal alu_op_s : alu_op_t;
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signal io_l_op_s : io_l_op_t;
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signal io_d_op_s : io_d_op_t;
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signal io_g_op_s : io_g_op_t;
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signal sio_op_s : sio_op_t;
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signal is_lbi_s : boolean;
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signal en_s : dw_t;
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signal skip_s,
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skip_lbi_s : boolean;
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signal in_s,
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il_s : dw_t;
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signal vdd_s : std_logic;
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signal gnd4_s : dw_t;
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begin
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-- dummies
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vdd_s <= '1';
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gnd4_s <= (others => '0');
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in_s <= (others => '0');
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il_s <= (others => '0');
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ck_en_s <= ck_en_i = '1';
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por_s <= por_n_i = '0';
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-----------------------------------------------------------------------------
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-- Clock generator
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-----------------------------------------------------------------------------
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clkgen_b : t400_clkgen
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generic map (
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opt_ck_div_g => opt_ck_div_g
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)
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port map (
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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por_i => por_s,
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phi1_o => phi1_s,
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out_en_o => out_en_s,
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in_en_o => in_en_s,
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icyc_en_o => icyc_en_s
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);
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-----------------------------------------------------------------------------
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-- Reset module
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-----------------------------------------------------------------------------
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reset_b : t400_reset
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port map (
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ck_i => ck_i,
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icyc_en_i => icyc_en_s,
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por_i => por_s,
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reset_n_i => reset_n_i,
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res_o => res_s
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);
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-----------------------------------------------------------------------------
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-- Program memory controller
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-----------------------------------------------------------------------------
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pmem_ctrl_b : t400_pmem_ctrl
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generic map (
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opt_type_g => opt_type_g
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)
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port map (
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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por_i => por_s,
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res_i => res_s,
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a_i => a_s,
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m_i => dm_data_i,
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op_i => pc_op_s,
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dec_data_i => dec_data_s,
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pc_o => pc_to_stack_s,
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pc_i => pc_from_stack_s,
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pm_addr_o => pm_addr_s
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);
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--
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pm_addr_o <= std_logic_vector(pm_addr_s);
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-----------------------------------------------------------------------------
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-- Data memory controller
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-----------------------------------------------------------------------------
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dmem_ctrl_b : t400_dmem_ctrl
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generic map (
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opt_type_g => opt_type_g
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)
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port map (
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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por_i => por_s,
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res_i => res_s,
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dmem_op_i => dmem_op_s,
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b_op_i => b_op_s,
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dec_data_i => dec_data_s,
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a_i => a_s,
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q_high_i => q_s(7 downto 4),
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b_o => b_s,
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dm_addr_o => dm_addr_o,
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dm_data_i => dm_data_i,
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dm_data_o => dm_data_o,
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dm_we_o => dm_we_o
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);
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-----------------------------------------------------------------------------
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-- Decoder
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-----------------------------------------------------------------------------
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decoder_b : t400_decoder
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generic map (
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opt_type_g => opt_type_g
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)
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port map (
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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por_i => por_s,
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res_i => res_s,
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out_en_i => out_en_s,
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in_en_i => in_en_s,
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icyc_en_i => icyc_en_s,
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pc_op_o => pc_op_s,
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stack_op_o => stack_op_s,
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dmem_op_o => dmem_op_s,
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b_op_o => b_op_s,
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skip_op_o => skip_op_s,
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alu_op_o => alu_op_s,
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io_l_op_o => io_l_op_s,
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io_d_op_o => io_d_op_s,
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io_g_op_o => io_g_op_s,
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sio_op_o => sio_op_s,
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dec_data_o => dec_data_s,
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is_lbi_o => is_lbi_s,
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en_o => en_s,
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skip_i => skip_s,
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skip_lbi_i => skip_lbi_s,
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pm_addr_i => pm_addr_s,
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pm_data_i => pm_data_i
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);
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-----------------------------------------------------------------------------
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296 |
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-- Skip logic
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297 |
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-----------------------------------------------------------------------------
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298 |
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skip_b : t400_skip
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port map (
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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por_i => por_s,
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res_i => res_s,
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op_i => skip_op_s,
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dec_data_i => dec_data_s,
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carry_i => carry_s,
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c_i => c_s,
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bd_i => b_s(bd_range_t),
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is_lbi_i => is_lbi_s,
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a_i => a_s,
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m_i => dm_data_i,
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g_i => io_g_i,
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tim_c_i => gnd4_s(0),
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skip_o => skip_s,
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skip_lbi_o => skip_lbi_s
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);
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318 |
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319 |
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-----------------------------------------------------------------------------
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320 |
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-- ALU
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321 |
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-----------------------------------------------------------------------------
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322 |
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alu_b : t400_alu
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port map (
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324 |
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ck_i => ck_i,
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ck_en_i => ck_en_s,
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326 |
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por_i => por_s,
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res_i => res_s,
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328 |
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op_i => alu_op_s,
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329 |
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m_i => dm_data_i,
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330 |
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dec_data_i => dec_data_s,
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331 |
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q_low_i => q_s(3 downto 0),
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332 |
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b_i => b_s,
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333 |
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g_i => io_g_i,
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in_i => in_s,
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335 |
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il_i => il_s,
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sio_i => sio_s,
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337 |
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a_o => a_s,
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338 |
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carry_o => carry_s,
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339 |
|
|
c_o => c_s
|
340 |
|
|
);
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
-----------------------------------------------------------------------------
|
344 |
|
|
-- Stack module
|
345 |
|
|
-----------------------------------------------------------------------------
|
346 |
|
|
stack_b : t400_stack
|
347 |
|
|
generic map (
|
348 |
|
|
opt_type_g => opt_type_g
|
349 |
|
|
)
|
350 |
|
|
port map (
|
351 |
|
|
ck_i => ck_i,
|
352 |
|
|
ck_en_i => ck_en_s,
|
353 |
|
|
por_i => por_s,
|
354 |
|
|
op_i => stack_op_s,
|
355 |
|
|
pc_i => pc_to_stack_s,
|
356 |
|
|
pc_o => pc_from_stack_s
|
357 |
|
|
);
|
358 |
|
|
|
359 |
|
|
|
360 |
|
|
-----------------------------------------------------------------------------
|
361 |
|
|
-- IO L module
|
362 |
|
|
-----------------------------------------------------------------------------
|
363 |
|
|
io_l_b : t400_io_l
|
364 |
|
|
generic map (
|
365 |
|
|
opt_out_type_7_g => opt_l_out_type_7_g,
|
366 |
|
|
opt_out_type_6_g => opt_l_out_type_6_g,
|
367 |
|
|
opt_out_type_5_g => opt_l_out_type_5_g,
|
368 |
|
|
opt_out_type_4_g => opt_l_out_type_4_g,
|
369 |
|
|
opt_out_type_3_g => opt_l_out_type_3_g,
|
370 |
|
|
opt_out_type_2_g => opt_l_out_type_2_g,
|
371 |
|
|
opt_out_type_1_g => opt_l_out_type_1_g,
|
372 |
|
|
opt_out_type_0_g => opt_l_out_type_0_g,
|
373 |
|
|
opt_microbus_g => opt_microbus_g
|
374 |
|
|
)
|
375 |
|
|
port map (
|
376 |
|
|
ck_i => ck_i,
|
377 |
|
|
ck_en_i => ck_en_s,
|
378 |
|
|
por_i => por_s,
|
379 |
|
|
op_i => io_l_op_s,
|
380 |
|
|
en2_i => en_s(2),
|
381 |
|
|
m_i => dm_data_i,
|
382 |
|
|
a_i => a_s,
|
383 |
|
|
pm_data_i => pm_data_i,
|
384 |
|
|
q_o => q_s,
|
385 |
|
|
cs_n_i => vdd_s,
|
386 |
|
|
rd_n_i => vdd_s,
|
387 |
|
|
wr_n_i => vdd_s,
|
388 |
|
|
io_l_i => io_l_i,
|
389 |
|
|
io_l_o => io_l_o,
|
390 |
|
|
io_l_en_o => io_l_en_o
|
391 |
|
|
);
|
392 |
|
|
|
393 |
|
|
|
394 |
|
|
-----------------------------------------------------------------------------
|
395 |
|
|
-- IO D module
|
396 |
|
|
-----------------------------------------------------------------------------
|
397 |
|
|
io_d_b : t400_io_d
|
398 |
|
|
generic map (
|
399 |
|
|
opt_out_type_3_g => opt_d_out_type_3_g,
|
400 |
|
|
opt_out_type_2_g => opt_d_out_type_2_g,
|
401 |
|
|
opt_out_type_1_g => opt_d_out_type_1_g,
|
402 |
|
|
opt_out_type_0_g => opt_d_out_type_0_g
|
403 |
|
|
)
|
404 |
|
|
port map (
|
405 |
|
|
ck_i => ck_i,
|
406 |
|
|
ck_en_i => ck_en_s,
|
407 |
|
|
por_i => por_s,
|
408 |
|
|
res_i => res_s,
|
409 |
|
|
op_i => io_d_op_s,
|
410 |
|
|
bd_i => b_s(bd_range_t),
|
411 |
|
|
io_d_o => io_d_o,
|
412 |
|
|
io_d_en_o => io_d_en_o
|
413 |
|
|
);
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
-----------------------------------------------------------------------------
|
417 |
|
|
-- IO G modle
|
418 |
|
|
-----------------------------------------------------------------------------
|
419 |
|
|
io_g_b : t400_io_g
|
420 |
|
|
generic map (
|
421 |
|
|
opt_out_type_3_g => opt_g_out_type_3_g,
|
422 |
|
|
opt_out_type_2_g => opt_g_out_type_2_g,
|
423 |
|
|
opt_out_type_1_g => opt_g_out_type_1_g,
|
424 |
|
|
opt_out_type_0_g => opt_g_out_type_0_g
|
425 |
|
|
)
|
426 |
|
|
port map (
|
427 |
|
|
ck_i => ck_i,
|
428 |
|
|
ck_en_i => ck_en_s,
|
429 |
|
|
por_i => por_s,
|
430 |
|
|
res_i => res_s,
|
431 |
|
|
op_i => io_g_op_s,
|
432 |
|
|
m_i => dm_data_i,
|
433 |
|
|
dec_data_i => dec_data_s,
|
434 |
|
|
io_g_o => io_g_o,
|
435 |
|
|
io_g_en_o => io_g_en_o
|
436 |
|
|
);
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
-----------------------------------------------------------------------------
|
440 |
|
|
-- SIO module
|
441 |
|
|
-----------------------------------------------------------------------------
|
442 |
|
|
sio_b : t400_sio
|
443 |
|
|
generic map (
|
444 |
|
|
opt_so_output_type_g => opt_so_output_type_g,
|
445 |
|
|
opt_sk_output_type_g => opt_sk_output_type_g
|
446 |
|
|
)
|
447 |
|
|
port map (
|
448 |
|
|
ck_i => ck_i,
|
449 |
|
|
ck_en_i => ck_en_s,
|
450 |
|
|
por_i => por_s,
|
451 |
|
|
res_i => res_s,
|
452 |
|
|
phi1_i => phi1_s,
|
453 |
|
|
out_en_i => out_en_s,
|
454 |
|
|
in_en_i => in_en_s,
|
455 |
|
|
op_i => sio_op_s,
|
456 |
|
|
en0_i => en_s(0),
|
457 |
|
|
en3_i => en_s(3),
|
458 |
|
|
a_i => a_s,
|
459 |
|
|
c_i => c_s,
|
460 |
|
|
sio_o => sio_s,
|
461 |
|
|
si_i => si_i,
|
462 |
|
|
so_o => so_o,
|
463 |
|
|
so_en_o => so_en_o,
|
464 |
|
|
sk_o => sk_o,
|
465 |
|
|
sk_en_o => sk_en_o
|
466 |
|
|
);
|
467 |
|
|
|
468 |
|
|
end struct;
|
469 |
|
|
|
470 |
|
|
|
471 |
|
|
-------------------------------------------------------------------------------
|
472 |
|
|
-- File History:
|
473 |
|
|
--
|
474 |
|
|
-- $Log: not supported by cvs2svn $
|
475 |
|
|
-------------------------------------------------------------------------------
|