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arniml |
-------------------------------------------------------------------------------
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--
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-- The IN port controller.
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--
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arniml |
-- $Id: t400_io_in.vhd,v 1.3 2006-05-27 19:14:18 arniml Exp $
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arniml |
--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t400/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t400_pack.all;
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entity t400_io_in is
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port (
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-- System Interface -------------------------------------------------------
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ck_i : in std_logic;
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ck_en_i : in boolean;
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por_i : in boolean;
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icyc_en_i : in boolean;
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in_en_i : in boolean;
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-- Control Interface ------------------------------------------------------
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op_i : in io_in_op_t;
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en1_i : in std_logic;
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-- Port Interface ---------------------------------------------------------
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io_in_i : in dw_t;
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in_o : out dw_t;
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int_o : out boolean
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);
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end t400_io_in;
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architecture rtl of t400_io_in is
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constant idx_in3_c : natural := 2;
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constant idx_in0_c : natural := 1;
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constant idx_int_c : natural := 0;
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type neg_edge_t is array (natural range 1 downto 0) of
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std_logic_vector(2 downto 0);
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signal neg_edge_q : neg_edge_t;
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signal neg_edge_s : std_logic_vector(2 downto 0);
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signal il_q : std_logic_vector(1 downto 0);
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signal int_q,
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int_icyc_q : boolean;
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begin
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-----------------------------------------------------------------------------
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-- Process seq
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--
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-- Purpose:
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-- Implements the sequential elements.
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--
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seq: process (ck_i, por_i)
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variable neg_edge_v : std_logic_vector(2 downto 0);
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begin
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if por_i then
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neg_edge_q <= (others => (others => '0'));
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il_q <= (others => '0');
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int_q <= false;
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int_icyc_q <= false;
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elsif ck_i'event and ck_i = '1' then
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-- negative edge detector filp-flops ------------------------------------
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neg_edge_v(idx_in3_c) := to_X01(io_in_i(3));
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neg_edge_v(idx_in0_c) := to_X01(io_in_i(0));
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neg_edge_v(idx_int_c) := to_X01(io_in_i(1));
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if in_en_i then
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neg_edge_q(0) <= neg_edge_v;
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neg_edge_q(1) <= neg_edge_q(0) or neg_edge_v;
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end if;
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-- IL latches -----------------------------------------------------------
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if in_en_i then
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if neg_edge_q(1)(idx_in3_c) = '1' and
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((neg_edge_q(0)(idx_in3_c) or neg_edge_v(idx_in3_c)) = '0') then
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il_q(1) <= '1';
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end if;
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if neg_edge_q(1)(idx_in0_c) = '1' and
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((neg_edge_q(0)(idx_in0_c) or neg_edge_v(idx_in0_c)) = '0') then
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il_q(0) <= '1';
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end if;
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end if;
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-- Interrupt trigger ----------------------------------------------------
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if in_en_i then
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if neg_edge_q(1)(idx_int_c) = '1' and
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((neg_edge_q(0)(idx_int_c) or neg_edge_v(idx_int_c)) = '0') then
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int_q <= true;
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end if;
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end if;
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if icyc_en_i then
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-- delay interrupt request until end of current instruction
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-- this ensures that the interrupt is valid for a full instruction
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-- (i.e. the next one)
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int_icyc_q <= int_q;
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end if;
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if ck_en_i then
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if op_i = IOIN_INIL then
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il_q <= (others => '0');
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end if;
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if op_i = IOIN_INTACK then
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int_q <= false;
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int_icyc_q <= false;
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end if;
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end if;
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end if;
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end process seq;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-----------------------------------------------------------------------------
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in_o <= il_q(1) & "00" & il_q(0)
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when op_i = IOIN_INIL else
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io_in_i;
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int_o <= int_icyc_q;
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end rtl;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2006/05/23 01:13:28 arniml
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-- + reset neg_edge flip-flops to '1'
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-- -> after por, a 1-to-0 edge is required to trigger the latches initially
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-- + use to_X01
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--
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-- Revision 1.1 2006/05/22 00:00:55 arniml
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-- initial check-in
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--
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arniml |
-------------------------------------------------------------------------------
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