OpenCores
URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [rtl/] [vhdl/] [t400_reset.vhd] - Blame information for rev 176

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 arniml
-------------------------------------------------------------------------------
2
--
3
-- The reset generation unit.
4
--
5
-- $Id: t400_reset.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
6
--
7
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
8
--
9
-- All rights reserved
10
--
11
-- Redistribution and use in source and synthezised forms, with or without
12
-- modification, are permitted provided that the following conditions are met:
13
--
14
-- Redistributions of source code must retain the above copyright notice,
15
-- this list of conditions and the following disclaimer.
16
--
17
-- Redistributions in synthesized form must reproduce the above copyright
18
-- notice, this list of conditions and the following disclaimer in the
19
-- documentation and/or other materials provided with the distribution.
20
--
21
-- Neither the name of the author nor the names of other contributors may
22
-- be used to endorse or promote products derived from this software without
23
-- specific prior written permission.
24
--
25
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
29
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35
-- POSSIBILITY OF SUCH DAMAGE.
36
--
37
-- Please report bugs to the author, but before you do so, please
38
-- make sure that this is not a derivative work and that
39
-- you have the latest version of this file.
40
--
41
-- The latest version of this file can be found at:
42
--      http://www.opencores.org/cvsweb.shtml/t400/
43
--
44
-------------------------------------------------------------------------------
45
 
46
library ieee;
47
use ieee.std_logic_1164.all;
48
 
49
entity t400_reset is
50
 
51
  port (
52
    -- System Interface -------------------------------------------------------
53
    ck_i      : in  std_logic;
54
    icyc_en_i : in  boolean;
55
    por_i     : in  boolean;
56
    -- Reset Interface --------------------------------------------------------
57
    reset_n_i : in  std_logic;
58
    res_o     : out boolean
59
  );
60
 
61
end t400_reset;
62
 
63
 
64
library ieee;
65
use ieee.numeric_std.all;
66
 
67
architecture rtl of t400_reset is
68
 
69
  type   res_state_t is (IDLE,
70
                         RES1, RES2,
71
                         RES_ACTIVE);
72
  signal res_state_q : res_state_t;
73
  signal res_q       : boolean;
74
 
75
begin
76
 
77
  -----------------------------------------------------------------------------
78
  -- Process res_fsm
79
  --
80
  -- Purpose:
81
  --   Implements the reset timing/controlling FSM.
82
  --   User's Guide chapter 2.3 requires that reset_n_i has to be low for
83
  --   at least 3 instruction cycle times until it initializes the CPU.
84
  --
85
  res_fsm: process (ck_i, por_i)
86
  begin
87
    if por_i then
88
      res_state_q <= IDLE;
89
      res_q       <= false;
90
 
91
    elsif ck_i'event and ck_i = '1' then
92
      res_q               <= false;
93
      if icyc_en_i then
94
        case res_state_q is
95
          when IDLE =>
96
            if reset_n_i = '0' then
97
              res_state_q <= RES1;
98
            end if;
99
 
100
          when RES1 =>
101
            if reset_n_i = '0' then
102
              res_state_q <= RES2;
103
            else
104
              res_state_q <= IDLE;
105
            end if;
106
 
107
          when RES2 =>
108
            if reset_n_i = '0' then
109
              res_state_q <= RES_ACTIVE;
110
            else
111
              res_state_q <= IDLE;
112
            end if;
113
 
114
          when RES_ACTIVE =>
115
            res_q         <= true;
116
            if reset_n_i = '1' then
117
              res_state_q <= IDLE;
118
            end if;
119
 
120
          when others =>
121
            res_state_q   <= IDLE;
122
 
123
        end case;
124
 
125
      end if;
126
 
127
    end if;
128
  end process res_fsm;
129
  --
130
  -----------------------------------------------------------------------------
131
 
132
 
133
  -----------------------------------------------------------------------------
134
  -- Output mapping
135
  -----------------------------------------------------------------------------
136
  res_o <= res_q;
137
 
138
end rtl;
139
 
140
 
141
-------------------------------------------------------------------------------
142
-- File History:
143
--
144
-- $Log: not supported by cvs2svn $
145
-------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.