1 |
156 |
arniml |
set_global_assignment -name TOP_LEVEL_ENTITY t421
|
2 |
|
|
# Copyright (C) 1991-2005 Altera Corporation
|
3 |
|
|
# Your use of Altera Corporation's design tools, logic functions
|
4 |
|
|
# and other software and tools, and its AMPP partner logic
|
5 |
|
|
# functions, and any output files any of the foregoing
|
6 |
|
|
# (including device programming or simulation files), and any
|
7 |
|
|
# associated documentation or information are expressly subject
|
8 |
|
|
# to the terms and conditions of the Altera Program License
|
9 |
|
|
# Subscription Agreement, Altera MegaCore Function License
|
10 |
|
|
# Agreement, or other applicable license agreement, including,
|
11 |
|
|
# without limitation, that your use is for the sole purpose of
|
12 |
|
|
# programming logic devices manufactured by Altera and sold by
|
13 |
|
|
# Altera or its authorized distributors. Please refer to the
|
14 |
|
|
# applicable agreement for further details.
|
15 |
|
|
|
16 |
|
|
|
17 |
|
|
# The default values for assignments are stored in the file
|
18 |
|
|
# t421_assignment_defaults.qdf
|
19 |
|
|
# If this file doesn't exist, and for assignments not listed, see file
|
20 |
|
|
# assignment_defaults.qdf
|
21 |
|
|
|
22 |
|
|
# Altera recommends that you do not modify this file. This
|
23 |
|
|
# file is updated automatically by the Quartus II software
|
24 |
|
|
# and any changes you make may be lost or overwritten.
|
25 |
|
|
|
26 |
|
|
|
27 |
|
|
# Project-Wide Assignments
|
28 |
|
|
# ========================
|
29 |
158 |
arniml |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.0 SP1"
|
30 |
156 |
arniml |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:20:14 April 27, 2008"
|
31 |
158 |
arniml |
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
|
32 |
156 |
arniml |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_opt_pack-p.vhd
|
33 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_clkgen.vhd
|
34 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_reset.vhd
|
35 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pack-p.vhd
|
36 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_pmem_ctrl.vhd
|
37 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_dmem_ctrl.vhd
|
38 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_comp_pack-p.vhd
|
39 |
166 |
arniml |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_mnemonic_pack-p.vhd
|
40 |
156 |
arniml |
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_decoder.vhd
|
41 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_skip.vhd
|
42 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_alu.vhd
|
43 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_stack.vhd
|
44 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_pack-p.vhd
|
45 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_l.vhd
|
46 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_d.vhd
|
47 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_g.vhd
|
48 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_io_in.vhd
|
49 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_sio.vhd
|
50 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_timer.vhd
|
51 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core.vhd
|
52 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/tech/generic/generic_ram_ena.vhd
|
53 |
|
|
set_global_assignment -name VHDL_FILE rom_t42x.vhd
|
54 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-e.vhd
|
55 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_rom-struct-a.vhd
|
56 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/tech/cyclone/t400_por.vhd
|
57 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/t400_core_comp_pack-p.vhd
|
58 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/tech/t400_tech_comp_pack-p.vhd
|
59 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t420_notri.vhd
|
60 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t400_system_comp_pack-p.vhd
|
61 |
|
|
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/system/t421.vhd
|
62 |
|
|
|
63 |
|
|
# Analysis & Synthesis Assignments
|
64 |
|
|
# ================================
|
65 |
|
|
set_global_assignment -name VHDL_INPUT_VERSION VHDL87
|
66 |
|
|
|
67 |
|
|
set_global_assignment -name FAMILY Cyclone
|
68 |
|
|
set_global_assignment -name DEVICE EP1C12Q240C8
|
69 |
|
|
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
|
70 |
|
|
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
|
71 |
|
|
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id ck_i
|
72 |
166 |
arniml |
set_instance_assignment -name CLOCK_SETTINGS ck_i -to ck_i
|
73 |
156 |
arniml |
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
|
74 |
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
75 |
159 |
arniml |
|
76 |
|
|
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
|