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arniml |
-------------------------------------------------------------------------------
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--
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-- T48 Microcontroller Core
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--
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arniml |
-- $Id: t48_core.vhd,v 1.4 2004-03-29 19:39:58 arniml Exp $
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arniml |
--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-- Limitations :
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-- =============
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--
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-- Compared to the original MCS-48 architecture, the following limitations
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-- apply:
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--
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arniml |
-- * Nibble-wide instructions addressing expander port implemented but
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-- not verified yet.
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arniml |
--
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-- * Single-step mode not implemented.
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-- Not selected for future implementation.
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--
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-- * Reading of internal Program Memory not implemented.
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-- Not selected for future implementation.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity t48_core is
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generic (
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-- divide XTAL1 by 3 to derive Clock States
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xtal_div_3_g : integer := 1;
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-- store mnemonic in flip-flops (registered-out)
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register_mnemonic_g : integer := 1;
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-- include the port 1 module
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include_port1_g : integer := 1;
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-- include the port 2 module
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include_port2_g : integer := 1;
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-- include the BUS module
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include_bus_g : integer := 1;
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-- include the timer module
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include_timer_g : integer := 1;
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-- state in which T1 is sampled (3 or 4)
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sample_t1_state_g : integer := 4
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);
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port (
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-- T48 Interface ----------------------------------------------------------
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arniml |
xtal_i : in std_logic;
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reset_i : in std_logic;
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t0_i : in std_logic;
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t0_o : out std_logic;
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t0_dir_o : out std_logic;
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int_n_i : in std_logic;
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ea_i : in std_logic;
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rd_n_o : out std_logic;
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psen_n_o : out std_logic;
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wr_n_o : out std_logic;
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ale_o : out std_logic;
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db_i : in std_logic_vector( 7 downto 0);
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db_o : out std_logic_vector( 7 downto 0);
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db_dir_o : out std_logic;
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t1_i : in std_logic;
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p2_i : in std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2_low_imp_o : out std_logic;
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p1_i : in std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_low_imp_o : out std_logic;
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prog_n_o : out std_logic;
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arniml |
-- Core Interface ---------------------------------------------------------
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arniml |
clk_i : in std_logic;
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en_clk_i : in std_logic;
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xtal3_o : out std_logic;
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dmem_addr_o : out std_logic_vector( 7 downto 0);
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dmem_we_o : out std_logic;
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dmem_data_i : in std_logic_vector( 7 downto 0);
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dmem_data_o : out std_logic_vector( 7 downto 0);
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pmem_addr_o : out std_logic_vector(11 downto 0);
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pmem_data_i : in std_logic_vector( 7 downto 0)
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arniml |
);
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end t48_core;
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use work.alu_pack.alu_op_t;
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use work.cond_branch_pack.branch_conditions_t;
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use work.cond_branch_pack.comp_value_t;
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use work.dmem_ctrl_pack.dmem_addr_ident_t;
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use work.pmem_ctrl_pack.pmem_addr_ident_t;
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use work.t48_comp_pack.all;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.word_t;
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use work.t48_pack.pmem_addr_t;
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use work.t48_pack.mstate_t;
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use work.t48_pack.to_stdLogic;
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use work.t48_pack.to_boolean;
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architecture struct of t48_core is
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signal t48_data_s : word_t;
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signal en_clk_s : boolean;
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-- ALU signals
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signal alu_data_s : word_t;
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signal alu_write_accu_s : boolean;
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signal alu_write_shadow_s : boolean;
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signal alu_write_temp_reg_s : boolean;
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signal alu_read_alu_s : boolean;
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signal alu_carry_s : std_logic;
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signal alu_aux_carry_s : std_logic;
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signal alu_op_s : alu_op_t;
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signal alu_use_carry_s : boolean;
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arniml |
signal alu_da_low_s : boolean;
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signal alu_da_high_s : boolean;
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signal alu_da_overflow_s : boolean;
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signal alu_p06_temp_reg_s : boolean;
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signal alu_p60_temp_reg_s : boolean;
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4 |
arniml |
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-- BUS signals
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signal bus_write_bus_s : boolean;
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signal bus_read_bus_s : boolean;
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signal bus_output_pcl_s : boolean;
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signal bus_bidir_bus_s : boolean;
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signal bus_data_s : word_t;
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-- Clock Controller signals
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signal clk_multi_cycle_s : boolean;
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signal clk_assert_psen_s : boolean;
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signal clk_assert_prog_s : boolean;
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signal clk_assert_rd_s : boolean;
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signal clk_assert_wr_s : boolean;
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signal clk_mstate_s : mstate_t;
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signal clk_second_cycle_s : boolean;
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signal psen_s : boolean;
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signal prog_s : boolean;
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signal rd_s : boolean;
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signal wr_s : boolean;
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signal ale_s : boolean;
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signal xtal3_s : boolean;
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-- Conditional Branch Logic signals
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signal cnd_compute_take_s : boolean;
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signal cnd_branch_cond_s : branch_conditions_t;
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signal cnd_take_branch_s : boolean;
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signal cnd_comp_value_s : comp_value_t;
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signal cnd_f1_s : std_logic;
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signal cnd_tf_s : std_logic;
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-- Data Memory Controller signals
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signal dm_write_dmem_addr_s : boolean;
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signal dm_write_dmem_s : boolean;
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signal dm_read_dmem_s : boolean;
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signal dm_addr_type_s : dmem_addr_ident_t;
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signal dm_data_s : word_t;
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-- Decoder signals
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signal dec_data_s : word_t;
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-- Port 1 signals
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signal p1_write_p1_s : boolean;
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signal p1_read_p1_s : boolean;
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signal p1_read_reg_s : boolean;
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signal p1_data_s : word_t;
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-- Port 2 signals
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signal p2_write_p2_s : boolean;
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signal p2_write_exp_s : boolean;
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signal p2_read_p2_s : boolean;
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signal p2_read_reg_s : boolean;
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arniml |
signal p2_read_exp_s : boolean;
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arniml |
signal p2_output_pch_s : boolean;
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signal p2_output_exp_s : boolean;
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signal p2_data_s : word_t;
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-- Program Memory Controller signals
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signal pm_write_pcl_s : boolean;
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signal pm_read_pcl_s : boolean;
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signal pm_write_pch_s : boolean;
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signal pm_read_pch_s : boolean;
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signal pm_read_pmem_s : boolean;
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signal pm_inc_pc_s : boolean;
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signal pm_write_pmem_addr_s : boolean;
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signal pm_data_s : word_t;
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signal pm_addr_type_s : pmem_addr_ident_t;
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signal pmem_addr_s : pmem_addr_t;
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-- PSW signals
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signal psw_read_psw_s : boolean;
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signal psw_read_sp_s : boolean;
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signal psw_write_psw_s : boolean;
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signal psw_write_sp_s : boolean;
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signal psw_carry_s : std_logic;
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signal psw_aux_carry_s : std_logic;
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signal psw_f0_s : std_logic;
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signal psw_bs_s : std_logic;
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signal psw_special_data_s : std_logic;
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signal psw_inc_stackp_s : boolean;
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signal psw_dec_stackp_s : boolean;
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signal psw_write_carry_s : boolean;
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signal psw_write_aux_carry_s : boolean;
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signal psw_write_f0_s : boolean;
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signal psw_write_bs_s : boolean;
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signal psw_data_s : word_t;
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-- Timer signals
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signal tim_overflow_s : boolean;
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signal tim_of_s : std_logic;
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signal tim_read_timer_s : boolean;
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signal tim_write_timer_s : boolean;
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signal tim_start_t_s : boolean;
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signal tim_start_cnt_s : boolean;
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signal tim_stop_tcnt_s : boolean;
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signal tim_data_s : word_t;
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begin
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-----------------------------------------------------------------------------
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-- Check generics for valid values.
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-----------------------------------------------------------------------------
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-- pragma translate_off
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assert include_timer_g = 0 or include_timer_g = 1
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report "include_timer_g must be either 1 or 0!"
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severity failure;
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assert include_port1_g = 0 or include_port1_g = 1
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report "include_port1_g must be either 1 or 0!"
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severity failure;
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assert include_port2_g = 0 or include_port2_g = 1
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report "include_port2_g must be either 1 or 0!"
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severity failure;
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271 |
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assert include_bus_g = 0 or include_bus_g = 1
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report "include_bus_g must be either 1 or 0!"
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severity failure;
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-- pragma translate_on
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en_clk_s <= to_boolean(en_clk_i);
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alu_b : alu
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port map (
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clk_i => clk_i,
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res_i => reset_i,
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en_clk_i => en_clk_s,
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data_i => t48_data_s,
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data_o => alu_data_s,
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286 |
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write_accu_i => alu_write_accu_s,
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write_shadow_i => alu_write_shadow_s,
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write_temp_reg_i => alu_write_temp_reg_s,
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read_alu_i => alu_read_alu_s,
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carry_i => psw_carry_s,
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291 |
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carry_o => alu_carry_s,
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292 |
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aux_carry_i => psw_aux_carry_s,
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293 |
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aux_carry_o => alu_aux_carry_s,
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294 |
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alu_op_i => alu_op_s,
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295 |
28 |
arniml |
use_carry_i => alu_use_carry_s,
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296 |
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da_low_i => alu_da_low_s,
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297 |
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da_high_i => alu_da_high_s,
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298 |
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da_overflow_o => alu_da_overflow_s,
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299 |
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p06_temp_reg_i => alu_p06_temp_reg_s,
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300 |
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p60_temp_reg_i => alu_p60_temp_reg_s
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301 |
4 |
arniml |
);
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302 |
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303 |
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bus_mux_b : bus_mux
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304 |
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port map (
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305 |
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alu_data_i => alu_data_s,
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306 |
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bus_data_i => bus_data_s,
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307 |
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dec_data_i => dec_data_s,
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dm_data_i => dm_data_s,
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pm_data_i => pm_data_s,
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310 |
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p1_data_i => p1_data_s,
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311 |
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p2_data_i => p2_data_s,
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psw_data_i => psw_data_s,
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313 |
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tim_data_i => tim_data_s,
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data_o => t48_data_s
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);
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316 |
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317 |
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clock_ctrl_b : clock_ctrl
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318 |
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generic map (
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319 |
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xtal_div_3_g => xtal_div_3_g
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320 |
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)
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321 |
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port map (
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322 |
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clk_i => clk_i,
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323 |
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xtal_i => xtal_i,
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324 |
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res_i => reset_i,
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325 |
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en_clk_i => en_clk_s,
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326 |
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xtal3_o => xtal3_s,
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327 |
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multi_cycle_i => clk_multi_cycle_s,
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328 |
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assert_psen_i => clk_assert_psen_s,
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329 |
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assert_prog_i => clk_assert_prog_s,
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330 |
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assert_rd_i => clk_assert_rd_s,
|
331 |
|
|
assert_wr_i => clk_assert_wr_s,
|
332 |
|
|
mstate_o => clk_mstate_s,
|
333 |
|
|
second_cycle_o => clk_second_cycle_s,
|
334 |
|
|
ale_o => ale_s,
|
335 |
|
|
psen_o => psen_s,
|
336 |
|
|
prog_o => prog_s,
|
337 |
|
|
rd_o => rd_s,
|
338 |
|
|
wr_o => wr_s
|
339 |
|
|
);
|
340 |
|
|
|
341 |
|
|
cond_branch_b : cond_branch
|
342 |
|
|
port map (
|
343 |
|
|
clk_i => clk_i,
|
344 |
|
|
res_i => reset_i,
|
345 |
|
|
en_clk_i => en_clk_s,
|
346 |
|
|
compute_take_i => cnd_compute_take_s,
|
347 |
|
|
branch_cond_i => cnd_branch_cond_s,
|
348 |
|
|
take_branch_o => cnd_take_branch_s,
|
349 |
|
|
accu_i => alu_data_s,
|
350 |
|
|
t0_i => To_X01Z(t0_i),
|
351 |
|
|
t1_i => To_X01Z(t1_i),
|
352 |
|
|
int_n_i => int_n_i,
|
353 |
|
|
f0_i => psw_f0_s,
|
354 |
|
|
f1_i => cnd_f1_s,
|
355 |
|
|
tf_i => cnd_tf_s,
|
356 |
|
|
carry_i => psw_carry_s,
|
357 |
|
|
comp_value_i => cnd_comp_value_s
|
358 |
|
|
);
|
359 |
|
|
|
360 |
|
|
use_db_bus: if include_bus_g = 1 generate
|
361 |
|
|
db_bus_b : db_bus
|
362 |
|
|
port map (
|
363 |
|
|
clk_i => clk_i,
|
364 |
|
|
res_i => reset_i,
|
365 |
|
|
en_clk_i => en_clk_s,
|
366 |
|
|
ea_i => ea_i,
|
367 |
|
|
data_i => t48_data_s,
|
368 |
|
|
data_o => bus_data_s,
|
369 |
|
|
write_bus_i => bus_write_bus_s,
|
370 |
|
|
read_bus_i => bus_read_bus_s,
|
371 |
|
|
output_pcl_i => bus_output_pcl_s,
|
372 |
|
|
bidir_bus_i => bus_bidir_bus_s,
|
373 |
|
|
pcl_i => pmem_addr_s(word_t'range),
|
374 |
|
|
db_i => db_i,
|
375 |
|
|
db_o => db_o,
|
376 |
|
|
db_dir_o => db_dir_o
|
377 |
|
|
);
|
378 |
|
|
end generate;
|
379 |
|
|
|
380 |
|
|
skip_db_bus: if include_bus_g = 0 generate
|
381 |
|
|
bus_data_s <= (others => bus_idle_level_c);
|
382 |
|
|
db_o <= (others => '0');
|
383 |
|
|
db_dir_o <= '0';
|
384 |
|
|
end generate;
|
385 |
|
|
|
386 |
|
|
decoder_b : decoder
|
387 |
|
|
generic map (
|
388 |
|
|
register_mnemonic_g => register_mnemonic_g
|
389 |
|
|
)
|
390 |
|
|
port map (
|
391 |
|
|
clk_i => clk_i,
|
392 |
|
|
res_i => reset_i,
|
393 |
|
|
en_clk_i => en_clk_s,
|
394 |
|
|
ea_i => ea_i,
|
395 |
|
|
ale_i => ale_s,
|
396 |
|
|
int_n_i => int_n_i,
|
397 |
|
|
t0_dir_o => t0_dir_o,
|
398 |
|
|
data_i => t48_data_s,
|
399 |
|
|
data_o => dec_data_s,
|
400 |
|
|
alu_write_accu_o => alu_write_accu_s,
|
401 |
|
|
alu_write_shadow_o => alu_write_shadow_s,
|
402 |
|
|
alu_write_temp_reg_o => alu_write_temp_reg_s,
|
403 |
|
|
alu_read_alu_o => alu_read_alu_s,
|
404 |
|
|
bus_write_bus_o => bus_write_bus_s,
|
405 |
|
|
bus_read_bus_o => bus_read_bus_s,
|
406 |
|
|
dm_write_dmem_addr_o => dm_write_dmem_addr_s,
|
407 |
|
|
dm_write_dmem_o => dm_write_dmem_s,
|
408 |
|
|
dm_read_dmem_o => dm_read_dmem_s,
|
409 |
|
|
p1_write_p1_o => p1_write_p1_s,
|
410 |
|
|
p1_read_p1_o => p1_read_p1_s,
|
411 |
|
|
pm_write_pcl_o => pm_write_pcl_s,
|
412 |
|
|
p2_write_p2_o => p2_write_p2_s,
|
413 |
|
|
p2_write_exp_o => p2_write_exp_s,
|
414 |
|
|
p2_read_p2_o => p2_read_p2_s,
|
415 |
|
|
pm_read_pcl_o => pm_read_pcl_s,
|
416 |
|
|
pm_write_pch_o => pm_write_pch_s,
|
417 |
|
|
pm_read_pch_o => pm_read_pch_s,
|
418 |
|
|
pm_read_pmem_o => pm_read_pmem_s,
|
419 |
|
|
psw_read_psw_o => psw_read_psw_s,
|
420 |
|
|
psw_read_sp_o => psw_read_sp_s,
|
421 |
|
|
psw_write_psw_o => psw_write_psw_s,
|
422 |
|
|
psw_write_sp_o => psw_write_sp_s,
|
423 |
|
|
alu_carry_i => alu_carry_s,
|
424 |
|
|
alu_op_o => alu_op_s,
|
425 |
|
|
alu_use_carry_o => alu_use_carry_s,
|
426 |
28 |
arniml |
alu_da_low_o => alu_da_low_s,
|
427 |
|
|
alu_da_high_o => alu_da_high_s,
|
428 |
|
|
alu_da_overflow_i => alu_da_overflow_s,
|
429 |
|
|
alu_p06_temp_reg_o => alu_p06_temp_reg_s,
|
430 |
|
|
alu_p60_temp_reg_o => alu_p60_temp_reg_s,
|
431 |
4 |
arniml |
bus_output_pcl_o => bus_output_pcl_s,
|
432 |
|
|
bus_bidir_bus_o => bus_bidir_bus_s,
|
433 |
|
|
clk_multi_cycle_o => clk_multi_cycle_s,
|
434 |
|
|
clk_assert_psen_o => clk_assert_psen_s,
|
435 |
|
|
clk_assert_prog_o => clk_assert_prog_s,
|
436 |
|
|
clk_assert_rd_o => clk_assert_rd_s,
|
437 |
|
|
clk_assert_wr_o => clk_assert_wr_s,
|
438 |
|
|
clk_mstate_i => clk_mstate_s,
|
439 |
|
|
clk_second_cycle_i => clk_second_cycle_s,
|
440 |
|
|
cnd_compute_take_o => cnd_compute_take_s,
|
441 |
|
|
cnd_branch_cond_o => cnd_branch_cond_s,
|
442 |
|
|
cnd_take_branch_i => cnd_take_branch_s,
|
443 |
|
|
cnd_comp_value_o => cnd_comp_value_s,
|
444 |
|
|
cnd_f1_o => cnd_f1_s,
|
445 |
|
|
cnd_tf_o => cnd_tf_s,
|
446 |
|
|
dm_addr_type_o => dm_addr_type_s,
|
447 |
|
|
tim_read_timer_o => tim_read_timer_s,
|
448 |
|
|
tim_write_timer_o => tim_write_timer_s,
|
449 |
|
|
tim_start_t_o => tim_start_t_s,
|
450 |
|
|
tim_start_cnt_o => tim_start_cnt_s,
|
451 |
|
|
tim_stop_tcnt_o => tim_stop_tcnt_s,
|
452 |
|
|
p1_read_reg_o => p1_read_reg_s,
|
453 |
|
|
p2_read_reg_o => p2_read_reg_s,
|
454 |
24 |
arniml |
p2_read_exp_o => p2_read_exp_s,
|
455 |
4 |
arniml |
p2_output_pch_o => p2_output_pch_s,
|
456 |
|
|
p2_output_exp_o => p2_output_exp_s,
|
457 |
|
|
pm_inc_pc_o => pm_inc_pc_s,
|
458 |
|
|
pm_write_pmem_addr_o => pm_write_pmem_addr_s,
|
459 |
|
|
pm_addr_type_o => pm_addr_type_s,
|
460 |
|
|
psw_special_data_o => psw_special_data_s,
|
461 |
|
|
psw_carry_i => psw_carry_s,
|
462 |
28 |
arniml |
psw_aux_carry_i => psw_aux_carry_s,
|
463 |
4 |
arniml |
psw_f0_i => psw_f0_s,
|
464 |
|
|
psw_inc_stackp_o => psw_inc_stackp_s,
|
465 |
|
|
psw_dec_stackp_o => psw_dec_stackp_s,
|
466 |
|
|
psw_write_carry_o => psw_write_carry_s,
|
467 |
|
|
psw_write_aux_carry_o => psw_write_aux_carry_s,
|
468 |
|
|
psw_write_f0_o => psw_write_f0_s,
|
469 |
|
|
psw_write_bs_o => psw_write_bs_s,
|
470 |
|
|
tim_overflow_i => tim_overflow_s
|
471 |
|
|
);
|
472 |
|
|
|
473 |
|
|
dmem_ctrl_b : dmem_ctrl
|
474 |
|
|
port map (
|
475 |
|
|
clk_i => clk_i,
|
476 |
|
|
res_i => reset_i,
|
477 |
|
|
en_clk_i => en_clk_s,
|
478 |
|
|
data_i => t48_data_s,
|
479 |
|
|
write_dmem_addr_i => dm_write_dmem_addr_s,
|
480 |
|
|
write_dmem_i => dm_write_dmem_s,
|
481 |
|
|
read_dmem_i => dm_read_dmem_s,
|
482 |
|
|
addr_type_i => dm_addr_type_s,
|
483 |
|
|
bank_select_i => psw_bs_s,
|
484 |
|
|
data_o => dm_data_s,
|
485 |
|
|
dmem_data_i => dmem_data_i,
|
486 |
|
|
dmem_addr_o => dmem_addr_o,
|
487 |
|
|
dmem_we_o => dmem_we_o,
|
488 |
|
|
dmem_data_o => dmem_data_o
|
489 |
|
|
);
|
490 |
|
|
|
491 |
|
|
use_timer: if include_timer_g = 1 generate
|
492 |
|
|
timer_b : timer
|
493 |
|
|
generic map (
|
494 |
|
|
sample_t1_state_g => sample_t1_state_g
|
495 |
|
|
)
|
496 |
|
|
port map (
|
497 |
|
|
clk_i => clk_i,
|
498 |
|
|
res_i => reset_i,
|
499 |
|
|
en_clk_i => en_clk_s,
|
500 |
|
|
t1_i => To_X01Z(t1_i),
|
501 |
|
|
clk_mstate_i => clk_mstate_s,
|
502 |
|
|
data_i => t48_data_s,
|
503 |
|
|
data_o => tim_data_s,
|
504 |
|
|
read_timer_i => tim_read_timer_s,
|
505 |
|
|
write_timer_i => tim_write_timer_s,
|
506 |
|
|
start_t_i => tim_start_t_s,
|
507 |
|
|
start_cnt_i => tim_start_cnt_s,
|
508 |
|
|
stop_tcnt_i => tim_stop_tcnt_s,
|
509 |
|
|
overflow_o => tim_of_s
|
510 |
|
|
);
|
511 |
|
|
end generate;
|
512 |
|
|
|
513 |
|
|
skip_timer: if include_timer_g = 0 generate
|
514 |
|
|
tim_data_s <= (others => bus_idle_level_c);
|
515 |
|
|
tim_of_s <= '0';
|
516 |
|
|
end generate;
|
517 |
|
|
|
518 |
|
|
tim_overflow_s <= to_boolean(tim_of_s);
|
519 |
|
|
|
520 |
|
|
use_p1: if include_port1_g = 1 generate
|
521 |
|
|
p1_b : p1
|
522 |
|
|
port map (
|
523 |
32 |
arniml |
clk_i => clk_i,
|
524 |
|
|
res_i => reset_i,
|
525 |
|
|
en_clk_i => en_clk_s,
|
526 |
|
|
data_i => t48_data_s,
|
527 |
|
|
data_o => p1_data_s,
|
528 |
|
|
write_p1_i => p1_write_p1_s,
|
529 |
|
|
read_p1_i => p1_read_p1_s,
|
530 |
|
|
read_reg_i => p1_read_reg_s,
|
531 |
|
|
p1_i => p1_i,
|
532 |
|
|
p1_o => p1_o,
|
533 |
|
|
p1_low_imp_o => p1_low_imp_o
|
534 |
4 |
arniml |
);
|
535 |
|
|
end generate;
|
536 |
|
|
|
537 |
|
|
skip_p1: if include_port1_g = 0 generate
|
538 |
32 |
arniml |
p1_data_s <= (others => bus_idle_level_c);
|
539 |
|
|
p1_o <= (others => '0');
|
540 |
|
|
p1_low_imp_o <= '0';
|
541 |
4 |
arniml |
end generate;
|
542 |
|
|
|
543 |
|
|
use_p2: if include_port2_g = 1 generate
|
544 |
|
|
p2_b : p2
|
545 |
|
|
port map (
|
546 |
|
|
clk_i => clk_i,
|
547 |
|
|
res_i => reset_i,
|
548 |
|
|
en_clk_i => en_clk_s,
|
549 |
|
|
data_i => t48_data_s,
|
550 |
|
|
data_o => p2_data_s,
|
551 |
|
|
write_p2_i => p2_write_p2_s,
|
552 |
|
|
write_exp_i => p2_write_exp_s,
|
553 |
|
|
read_p2_i => p2_read_p2_s,
|
554 |
|
|
read_reg_i => p2_read_reg_s,
|
555 |
24 |
arniml |
read_exp_i => p2_read_exp_s,
|
556 |
4 |
arniml |
output_pch_i => p2_output_pch_s,
|
557 |
|
|
output_exp_i => p2_output_exp_s,
|
558 |
|
|
pch_i => pmem_addr_s(11 downto 8),
|
559 |
|
|
p2_i => p2_i,
|
560 |
|
|
p2_o => p2_o,
|
561 |
32 |
arniml |
p2_low_imp_o => p2_low_imp_o
|
562 |
4 |
arniml |
);
|
563 |
|
|
end generate;
|
564 |
|
|
|
565 |
|
|
skip_p2: if include_port2_g = 0 generate
|
566 |
32 |
arniml |
p2_data_s <= (others => bus_idle_level_c);
|
567 |
|
|
p2_o <= (others => '0');
|
568 |
|
|
p2_low_imp_o <= '0';
|
569 |
4 |
arniml |
end generate;
|
570 |
|
|
|
571 |
|
|
pmem_ctrl_b : pmem_ctrl
|
572 |
|
|
port map (
|
573 |
|
|
clk_i => clk_i,
|
574 |
|
|
res_i => reset_i,
|
575 |
|
|
en_clk_i => en_clk_s,
|
576 |
|
|
data_i => t48_data_s,
|
577 |
|
|
data_o => pm_data_s,
|
578 |
|
|
write_pcl_i => pm_write_pcl_s,
|
579 |
|
|
read_pcl_i => pm_read_pcl_s,
|
580 |
|
|
write_pch_i => pm_write_pch_s,
|
581 |
|
|
read_pch_i => pm_read_pch_s,
|
582 |
|
|
inc_pc_i => pm_inc_pc_s,
|
583 |
|
|
write_pmem_addr_i => pm_write_pmem_addr_s,
|
584 |
|
|
addr_type_i => pm_addr_type_s,
|
585 |
|
|
read_pmem_i => pm_read_pmem_s,
|
586 |
|
|
pmem_addr_o => pmem_addr_s,
|
587 |
|
|
pmem_data_i => pmem_data_i
|
588 |
|
|
);
|
589 |
|
|
|
590 |
|
|
psw_b : psw
|
591 |
|
|
port map (
|
592 |
|
|
clk_i => clk_i,
|
593 |
|
|
res_i => reset_i,
|
594 |
|
|
en_clk_i => en_clk_s,
|
595 |
|
|
data_i => t48_data_s,
|
596 |
|
|
data_o => psw_data_s,
|
597 |
|
|
read_psw_i => psw_read_psw_s,
|
598 |
|
|
read_sp_i => psw_read_sp_s,
|
599 |
|
|
write_psw_i => psw_write_psw_s,
|
600 |
|
|
write_sp_i => psw_write_sp_s,
|
601 |
|
|
special_data_i => psw_special_data_s,
|
602 |
|
|
inc_stackp_i => psw_inc_stackp_s,
|
603 |
|
|
dec_stackp_i => psw_dec_stackp_s,
|
604 |
|
|
write_carry_i => psw_write_carry_s,
|
605 |
|
|
write_aux_carry_i => psw_write_aux_carry_s,
|
606 |
|
|
write_f0_i => psw_write_f0_s,
|
607 |
|
|
write_bs_i => psw_write_bs_s,
|
608 |
|
|
carry_o => psw_carry_s,
|
609 |
28 |
arniml |
aux_carry_i => alu_aux_carry_s,
|
610 |
4 |
arniml |
aux_carry_o => psw_aux_carry_s,
|
611 |
|
|
f0_o => psw_f0_s,
|
612 |
|
|
bs_o => psw_bs_s
|
613 |
|
|
);
|
614 |
|
|
|
615 |
|
|
|
616 |
|
|
-----------------------------------------------------------------------------
|
617 |
|
|
-- Output Mapping.
|
618 |
|
|
-----------------------------------------------------------------------------
|
619 |
|
|
ale_o <= to_stdLogic(ale_s);
|
620 |
|
|
t0_o <= clk_i;
|
621 |
|
|
psen_n_o <= to_stdLogic(not psen_s);
|
622 |
|
|
prog_n_o <= to_stdLogic(not prog_s);
|
623 |
|
|
rd_n_o <= to_stdLogic(not rd_s);
|
624 |
|
|
wr_n_o <= to_stdLogic(not wr_s);
|
625 |
|
|
xtal3_o <= to_stdLogic(xtal3_s);
|
626 |
|
|
pmem_addr_o <= pmem_addr_s;
|
627 |
|
|
|
628 |
|
|
end struct;
|
629 |
|
|
|
630 |
|
|
|
631 |
|
|
-------------------------------------------------------------------------------
|
632 |
|
|
-- File History:
|
633 |
|
|
--
|
634 |
|
|
-- $Log: not supported by cvs2svn $
|
635 |
32 |
arniml |
-- Revision 1.3 2004/03/28 21:27:50 arniml
|
636 |
|
|
-- update wiring for DA support
|
637 |
|
|
--
|
638 |
28 |
arniml |
-- Revision 1.2 2004/03/28 13:13:20 arniml
|
639 |
|
|
-- connect control signal for Port 2 expander
|
640 |
|
|
--
|
641 |
24 |
arniml |
-- Revision 1.1 2004/03/23 21:31:53 arniml
|
642 |
|
|
-- initial check-in
|
643 |
4 |
arniml |
--
|
644 |
|
|
-------------------------------------------------------------------------------
|