Subversion Repositories t48

-------------------------------------------------------------------------------

--

-- The Decoder unit.

-- It decodes the instruction opcodes and executes them.

--

-- $Id: decoder.vhd,v 1.4 2004-04-04 14:18:53 arniml Exp $

--

-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)

--

-- All rights reserved

--

-- Redistribution and use in source and synthezised forms, with or without

-- modification, are permitted provided that the following conditions are met:

--

-- Redistributions of source code must retain the above copyright notice,

-- this list of conditions and the following disclaimer.

--

-- Redistributions in synthesized form must reproduce the above copyright

-- notice, this list of conditions and the following disclaimer in the

-- documentation and/or other materials provided with the distribution.

--

-- Neither the name of the author nor the names of other contributors may

-- be used to endorse or promote products derived from this software without

-- specific prior written permission.

--

-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE

-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

-- POSSIBILITY OF SUCH DAMAGE.

--

-- Please report bugs to the author, but before you do so, please

-- make sure that this is not a derivative work and that

-- you have the latest version of this file.

--

-- The latest version of this file can be found at:

--      http://www.opencores.org/cvsweb.shtml/t48/

--

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use work.t48_pack.word_t;

use work.t48_pack.mstate_t;

use work.alu_pack.alu_op_t;

use work.cond_branch_pack.all;

use work.dmem_ctrl_pack.all;

use work.pmem_ctrl_pack.all;

entity decoder is

  generic (

    -- store mnemonic in flip-flops (registered-out)

    register_mnemonic_g   : integer := 1

  );

  port (

    -- Global Interface -------------------------------------------------------

    clk_i                  : in  std_logic;

    res_i                  : in  std_logic;

    en_clk_i               : in  boolean;

    ea_i                   : in  std_logic;

    ale_i                  : in  boolean;

    int_n_i                : in  std_logic;

    t0_dir_o               : out std_logic;

    -- T48 Bus Interface ------------------------------------------------------

    data_i                 : in  word_t;

    data_o                 : out word_t;

    stack_high_o           : out boolean;

    alu_write_accu_o       : out boolean;

    alu_write_shadow_o     : out boolean;

    alu_write_temp_reg_o   : out boolean;

    alu_read_alu_o         : out boolean;

    bus_write_bus_o        : out boolean;

    bus_read_bus_o         : out boolean;

    dm_write_dmem_addr_o   : out boolean;

    dm_write_dmem_o        : out boolean;

    dm_read_dmem_o         : out boolean;

    p1_write_p1_o          : out boolean;

    p1_read_p1_o           : out boolean;

    p2_write_p2_o          : out boolean;

    p2_write_exp_o         : out boolean;

    p2_read_p2_o           : out boolean;

    p2_read_exp_o          : out boolean;

    pm_write_pcl_o         : out boolean;

    pm_read_pcl_o          : out boolean;

    pm_write_pch_o         : out boolean;

    pm_read_pch_o          : out boolean;

    pm_read_pmem_o         : out boolean;

    psw_read_psw_o         : out boolean;

    psw_read_sp_o          : out boolean;

    psw_write_psw_o        : out boolean;

    psw_write_sp_o         : out boolean;

    -- ALU Interface ----------------------------------------------------------

    alu_carry_i            : in  std_logic;

    alu_op_o               : out alu_op_t;

    alu_use_carry_o        : out boolean;

    alu_da_low_o           : out boolean;

    alu_da_high_o          : out boolean;

    alu_accu_low_o         : out boolean;

    alu_p06_temp_reg_o     : out boolean;

    alu_p60_temp_reg_o     : out boolean;

    alu_da_overflow_i      : in  boolean;

    -- BUS Interface ----------------------------------------------------------

    bus_output_pcl_o       : out boolean;

    bus_bidir_bus_o        : out boolean;

    -- Clock Controller Interface ---------------------------------------------

    clk_multi_cycle_o      : out boolean;

    clk_assert_psen_o      : out boolean;

    clk_assert_prog_o      : out boolean;

    clk_assert_rd_o        : out boolean;

    clk_assert_wr_o        : out boolean;

    clk_mstate_i           : in  mstate_t;

    clk_second_cycle_i     : in  boolean;

    -- Conditional Branch Logic Interface -------------------------------------

    cnd_compute_take_o     : out boolean;

    cnd_branch_cond_o      : out branch_conditions_t;

    cnd_take_branch_i      : in  boolean;

    cnd_comp_value_o       : out comp_value_t;

    cnd_f1_o               : out std_logic;

    cnd_tf_o               : out std_logic;

    -- Data Memory Controller Interface ---------------------------------------

    dm_addr_type_o         : out dmem_addr_ident_t;

    -- Port 1 Interface -------------------------------------------------------

    p1_read_reg_o          : out boolean;

    -- Port 2 Interface -------------------------------------------------------

    p2_read_reg_o          : out boolean;

    p2_output_pch_o        : out boolean;

    p2_output_exp_o        : out boolean;

    -- Program Memory Controller Interface ------------------------------------

    pm_inc_pc_o            : out boolean;

    pm_write_pmem_addr_o   : out boolean;

    pm_addr_type_o         : out pmem_addr_ident_t;

    -- Program Status Word Interface ------------------------------------------

    psw_special_data_o     : out std_logic;

    psw_carry_i            : in  std_logic;

    psw_aux_carry_i        : in  std_logic;

    psw_f0_i               : in  std_logic;

    psw_inc_stackp_o       : out boolean;

    psw_dec_stackp_o       : out boolean;

    psw_write_carry_o      : out boolean;

    psw_write_aux_carry_o  : out boolean;

    psw_write_f0_o         : out boolean;

    psw_write_bs_o         : out boolean;

    -- Timer Interface --------------------------------------------------------

    tim_read_timer_o       : out boolean;

    tim_write_timer_o      : out boolean;

    tim_start_t_o          : out boolean;

    tim_start_cnt_o        : out boolean;

    tim_stop_tcnt_o        : out boolean;

    tim_overflow_i         : in  boolean

  );

end decoder;

use work.t48_pack.all;

use work.alu_pack.all;

use work.decoder_pack.all;

use work.t48_comp_pack.opc_decoder;

use work.t48_comp_pack.int;

architecture rtl of decoder is

  -- Opcode Decoder

  signal opc_multi_cycle_s : boolean;

  signal opc_read_bus_s    : boolean;

  signal opc_inj_int_s     : boolean;

  signal opc_opcode_s      : word_t;

  signal opc_mnemonic_s    : mnemonic_t;

  signal last_cycle_s      : boolean;

  -- state translators

  signal assert_psen_s     : boolean;

  -- branch taken handshake

  signal branch_taken_s,

         branch_taken_q        : boolean;

  signal pm_inc_pc_s           : boolean;

  signal pm_write_pmem_addr_s  : boolean;

  -- additional signal to increment PC during CALL

  signal add_inc_pc_s          : boolean;

  -- addtional signal to set PC during RET(R)

  signal add_write_pmem_addr_s : boolean;

  -- Flag 1

  signal clear_f1_s,

         cpl_f1_s          : boolean;

  signal f1_q              : std_logic;

  -- memory bank select

  signal clear_mb_s,

         set_mb_s          : boolean;

  signal mb_q              : std_logic;

  -- T0 direction selection

  signal ent0_clk_s        : boolean;

  signal t0_dir_q          : std_logic;

  signal data_s            : word_t;

  signal read_dec_s        : boolean;

  signal tf_s              : std_logic;

  signal bus_read_bus_s    : boolean;

  signal add_read_bus_s    : boolean;

  signal dm_write_dmem_s   : boolean;

  -- interrupt handling

  signal jtf_executed_s    : boolean;

  signal en_tcnti_s        : boolean;

  signal dis_tcnti_s       : boolean;

  signal en_i_s            : boolean;

  signal dis_i_s           : boolean;

  signal tim_int_s         : boolean;

  signal retr_executed_s   : boolean;

  signal int_executed_s    : boolean;

  signal int_pending_s     : boolean;

  -- pragma translate_off

  signal istrobe_s         : std_logic;

  -- pragma translate_on

begin

  -----------------------------------------------------------------------------

  -- Opcode Decoder

  -----------------------------------------------------------------------------

  opc_decoder_b : opc_decoder

    generic map (

      register_mnemonic_g => register_mnemonic_g

    )

    port map (

      clk_i         => clk_i,

      res_i         => res_i,

      en_clk_i      => en_clk_i,

      data_i        => data_i,

      read_bus_i    => opc_read_bus_s,

      inj_int_i     => opc_inj_int_s,

      opcode_o      => opc_opcode_s,

      mnemonic_o    => opc_mnemonic_s,

      multi_cycle_o => opc_multi_cycle_s

    );

  -----------------------------------------------------------------------------

  -- Interrupt Controller.

  -----------------------------------------------------------------------------

  int_b : int

    port map (

      clk_i           => clk_i,

      res_i           => res_i,

      en_clk_i        => en_clk_i,

      clk_mstate_i    => clk_mstate_i,

      jtf_executed_i  => jtf_executed_s,

      tim_overflow_i  => tim_overflow_i,

      tf_o            => tf_s,

      en_tcnti_i      => en_tcnti_s,

      dis_tcnti_i     => dis_tcnti_s,

      int_n_i         => int_n_i,

      ale_i           => ale_i,

      last_cycle_i    => last_cycle_s,

      en_i_i          => en_i_s,

      dis_i_i         => dis_i_s,

      ext_int_o       => open,

      tim_int_o       => tim_int_s,

      retr_executed_i => retr_executed_s,

      int_executed_i  => int_executed_s,

      int_pending_o   => int_pending_s

    );

  last_cycle_s <= not opc_multi_cycle_s or

                  (opc_multi_cycle_s and clk_second_cycle_i);

  -----------------------------------------------------------------------------

  -- Process machine_cycle

  --

  -- Purpose:

  --   Generates the control signals that are basically needed for the

  --   handling of a machine cycle.

  --

  machine_cycle: process (clk_mstate_i,

                          clk_second_cycle_i,

                          ea_i,

                          assert_psen_s,

                          branch_taken_q,

                          int_pending_s)

   variable need_address_v      : boolean;

  begin

    -- default assignments

    clk_assert_psen_o    <= false;

    pm_inc_pc_s          <= false;

    pm_write_pmem_addr_s <= false;

    pm_read_pmem_o       <= false;

    bus_output_pcl_o     <= false;

    p2_output_pch_o      <= false;

    opc_read_bus_s       <= false;

    opc_inj_int_s        <= false;

    bus_read_bus_s       <= false;

    need_address_v    := not clk_second_cycle_i or

                         (clk_second_cycle_i and assert_psen_s);

    case clk_mstate_i is

      when MSTATE1 =>

        if need_address_v and not int_pending_s then

          if ea_i = '0' then

            pm_read_pmem_o  <= true;

          else

            bus_read_bus_s  <= true;

          end if;

        end if;

        if not clk_second_cycle_i then

          if not int_pending_s then

            opc_read_bus_s  <= true;

          else

            opc_inj_int_s   <= true;    -- inject interrupt call

          end if;

        end if;

      when MSTATE2 =>

        if need_address_v and not branch_taken_q and

           not int_pending_s then

          pm_inc_pc_s       <= true;

        end if;

      when MSTATE3 =>

        if need_address_v then

          pm_write_pmem_addr_s <= true;

          if ea_i = '1' then

            bus_output_pcl_o   <= true;

          end if;

        end if;

      when MSTATE4 =>

        if need_address_v and ea_i = '1' then

          clk_assert_psen_o <= true;

          p2_output_pch_o  <= true;

        end if;

      when MSTATE5 =>

        if need_address_v and ea_i = '1' then

          clk_assert_psen_o <= true;

        end if;

      when others =>

        -- pragma translate_off

        assert false

          report "Unkown machine state!"

          severity error;

        -- pragma translate_on

    end case;

  end process machine_cycle;

  --

  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------

  -- Process decode

  --

  -- Purpose:

  --   Indentifies each single instruction and steps through the related

  --   execution sequence.

  --

  decode: process (alu_carry_i,

                   psw_aux_carry_i,

                   alu_da_overflow_i,

                   clk_mstate_i,

                   clk_second_cycle_i,

                   cnd_take_branch_i,

                   opc_opcode_s,

                   opc_mnemonic_s,

                   data_i,

                   psw_carry_i,

                   psw_f0_i,

                   f1_q,

                   mb_q,

                   tim_int_s,

                   int_pending_s)

    procedure address_indirect_3_f is

    begin

      -- apply dmem address from selected register for indirect mode

      if opc_opcode_s(3) = '0' then

        dm_read_dmem_o       <= true;

        dm_write_dmem_addr_o <= true;

        dm_addr_type_o       <= DM_PLAIN;

      end if;

    end;

    procedure and_or_xor_add_4_f is

    begin

      -- write dmem contents to Temp Reg

      dm_read_dmem_o         <= true;

      alu_write_temp_reg_o   <= true;

    end;

    procedure and_or_xor_add_5_f (alu_op : alu_op_t) is

    begin

      -- perform ALU operation and store in Accumulator

      alu_op_o               <= alu_op;

      alu_read_alu_o         <= true;

      alu_write_accu_o       <= true;

    end;

    procedure cond_jump_c2_m1_f is

    begin

      -- store address in Program Counter low byte if branch has to

      -- be taken

      if clk_mstate_i = MSTATE1 and cnd_take_branch_i then

        pm_write_pcl_o       <= true;

        branch_taken_s       <= true;

      end if;

    end;

  begin

    -- default assignments

    data_s                 <= (others => '-');

    read_dec_s             <= false;

    branch_taken_s         <= false;

    clear_f1_s             <= false;

    cpl_f1_s               <= false;

    clear_mb_s             <= false;

    set_mb_s               <= false;

    add_inc_pc_s           <= false;

    assert_psen_s          <= false;

    stack_high_o           <= false;

    alu_write_accu_o       <= false;

    alu_write_shadow_o     <= false;

    alu_write_temp_reg_o   <= false;

    alu_p06_temp_reg_o     <= false;

    alu_p60_temp_reg_o     <= false;

    alu_read_alu_o         <= false;

    bus_write_bus_o        <= false;

    bus_bidir_bus_o        <= false;

    dm_write_dmem_addr_o   <= false;

    dm_write_dmem_s        <= false;

    dm_read_dmem_o         <= false;

    pm_write_pcl_o         <= false;

    pm_read_pcl_o          <= false;

    pm_write_pch_o         <= false;

    pm_read_pch_o          <= false;

    pm_addr_type_o         <= PM_PC;

    psw_read_psw_o         <= false;

    psw_read_sp_o          <= false;

    psw_write_psw_o        <= false;

    psw_write_sp_o         <= false;

    alu_op_o               <= ALU_NOP;

    alu_use_carry_o        <= false;

    alu_da_low_o           <= false;

    alu_da_high_o          <= false;

    alu_accu_low_o         <= false;

    clk_assert_prog_o      <= false;

    clk_assert_rd_o        <= false;

    clk_assert_wr_o        <= false;

    cnd_branch_cond_o      <= COND_ON_BIT;

    cnd_compute_take_o     <= false;

    cnd_comp_value_o       <= opc_opcode_s(7 downto 5);

    dm_addr_type_o         <= DM_REG;

    tim_read_timer_o       <= false;

    tim_write_timer_o      <= false;

    tim_start_t_o          <= false;

    tim_start_cnt_o        <= false;

    tim_stop_tcnt_o        <= false;

    p1_write_p1_o          <= false;

    p1_read_p1_o           <= false;

    p1_read_reg_o          <= false;

    p2_write_p2_o          <= false;

    p2_write_exp_o         <= false;

    p2_read_p2_o           <= false;

    p2_read_reg_o          <= false;

    p2_read_exp_o          <= false;

    p2_output_exp_o        <= false;

    psw_special_data_o     <= '0';

    psw_inc_stackp_o       <= false;

    psw_dec_stackp_o       <= false;

    psw_write_carry_o      <= false;

    psw_write_aux_carry_o  <= false;

    psw_write_f0_o         <= false;

    psw_write_bs_o         <= false;

    jtf_executed_s         <= false;

    en_tcnti_s             <= false;

    dis_tcnti_s            <= false;

    en_i_s                 <= false;

    dis_i_s                <= false;

    retr_executed_s        <= false;

    int_executed_s         <= false;

    add_write_pmem_addr_s  <= false;

    ent0_clk_s             <= false;

    add_read_bus_s         <= false;

    -- prepare potential register indirect address mode

    if not clk_second_cycle_i and clk_mstate_i = MSTATE2 then

      data_s               <= (others => '0');

      if opc_opcode_s(3) = '1' then

        data_s(2 downto 0) <= opc_opcode_s(2 downto 0);

      else

        data_s(2 downto 0) <= "00" & opc_opcode_s(0);

      end if;

      read_dec_s           <= true;

      dm_write_dmem_addr_o <= true;

      dm_addr_type_o       <= DM_REG;

    end if;

    case opc_mnemonic_s is

      -- Mnemonic ADD ---------------------------------------------------------

      when MN_ADD =>

        case clk_mstate_i is

          -- read RAM once for indirect address mode

          when MSTATE3 =>

            address_indirect_3_f;

          -- store data from RAM to Temp Reg

          when MSTATE4 =>

            and_or_xor_add_4_f;

          -- perform ADD and store in Accumulator

          when MSTATE5 =>

            and_or_xor_add_5_f(alu_op => ALU_ADD);

            if opc_opcode_s(4) = '1' then

              alu_use_carry_o     <= true;

            end if;

            psw_special_data_o    <= alu_carry_i;

            psw_write_carry_o     <= true;

            psw_write_aux_carry_o <= true;

          when others =>

            null;

        end case;

      -- Mnemonic ADD_A_DATA --------------------------------------------------

      when MN_ADD_A_DATA =>

        assert_psen_s               <= true;

        if clk_second_cycle_i then

          case clk_mstate_i is

            -- write Temp Reg when contents of Program Memory is on bus

            when MSTATE1 =>

              alu_write_temp_reg_o  <= true;

            -- perform ADD and store in Accumulator

            when MSTATE3 =>

              and_or_xor_add_5_f(alu_op => ALU_ADD);

              if opc_opcode_s(4) = '1' then

                alu_use_carry_o     <= true;

              end if;

              psw_special_data_o    <= alu_carry_i;

              psw_write_carry_o     <= true;

              psw_write_aux_carry_o <= true;

            when others =>

              null;

          end case;

        end if;

      -- Mnemonic ANL ---------------------------------------------------------

      when MN_ANL =>

        case clk_mstate_i is

          -- read RAM once for indirect address mode

          when MSTATE3 =>

            address_indirect_3_f;

          -- store data from RAM to Temp Reg

          when MSTATE4 =>

            and_or_xor_add_4_f;

          -- perform AND and store in Accumulator

          when MSTATE5 =>

            and_or_xor_add_5_f(alu_op => ALU_AND);

          when others =>

            null;

        end case;

      -- Mnemonic ANL_A_DATA --------------------------------------------------

      when MN_ANL_A_DATA =>

        assert_psen_s              <= true;

        if clk_second_cycle_i then

          case clk_mstate_i is

            -- write Temp Reg when contents of Program Memory is on bus

            when MSTATE1 =>

              alu_write_temp_reg_o <= true;

            -- perform AND and store in Accumulator

            when MSTATE3 =>

              and_or_xor_add_5_f(alu_op => ALU_AND);

            when others =>

              null;

          end case;

        end if;

      -- Mnemonic ANL_EXT -----------------------------------------------------

      when MN_ANL_EXT =>

        assert_psen_s            <= true;

        if not clk_second_cycle_i then

          -- read port to Temp Reg

          if clk_mstate_i = MSTATE5 then

            if opc_opcode_s(1 downto 0) = "00" then

              add_read_bus_s     <= true;

            elsif opc_opcode_s(1) = '0' then

              p1_read_p1_o       <= true;

              p1_read_reg_o      <= true;

            else

              p2_read_p2_o       <= true;

              p2_read_reg_o      <= true;

            end if;

            alu_write_temp_reg_o <= true;

          end if;

        else

          case clk_mstate_i is

            -- write shadow Accumulator when contents of Program Memory is

            -- on bus

            when MSTATE1 =>

              alu_write_shadow_o <= true;

            -- loop shadow Accumulator through ALU to prevent update from

            -- real Accumulator

            when MSTATE2 =>

              alu_read_alu_o     <= true;

              alu_write_shadow_o <= true;

            -- write result of AND operation back to port

            when MSTATE3 =>

              alu_op_o           <= ALU_AND;

              alu_read_alu_o     <= true;

              if opc_opcode_s(1 downto 0) = "00" then

                bus_write_bus_o  <= true;

              elsif opc_opcode_s(1) = '0' then

                p1_write_p1_o    <= true;

              else

                p2_write_p2_o    <= true;

              end if;

            when others =>

              null;

          end case;

        end if;

      -- Mnemonic CALL --------------------------------------------------------

      when MN_CALL =>

        assert_psen_s              <= true;

        if not clk_second_cycle_i then

          case clk_mstate_i is

            -- read Stack Pointer and address Data Memory for low byte

            -- also increment Program Counter to point to next instruction

            when MSTATE3 =>

              psw_read_sp_o        <= true;

              dm_write_dmem_addr_o <= true;

              dm_addr_type_o       <= DM_STACK;

              -- only increment PC if this is not an injected CALL

              -- injected CALLS are not located in Program Memory,

              -- the PC points already to the instruction to be executed

              -- after the interrupt

              if not int_pending_s then

                add_inc_pc_s       <= true;

              end if;

            -- store Program Counter low byte on stack

            when MSTATE4 =>

              pm_read_pcl_o        <= true;

              dm_write_dmem_s      <= true;

            -- store Program Counter high byte and PSW on stack

            -- increment Stack pointer

            when MSTATE5 =>

              psw_read_psw_o       <= true;

              pm_read_pch_o        <= true;

              dm_write_dmem_addr_o <= true;

              dm_addr_type_o       <= DM_STACK_HIGH;

              dm_write_dmem_s      <= true;

              psw_inc_stackp_o     <= true;

            when others =>

              null;

          end case;

        else

          case clk_mstate_i is

            -- store address in Program Counter low byte

            when MSTATE1 =>

              pm_write_pcl_o       <= true;

              branch_taken_s       <= true;

              if int_pending_s then

                -- apply low part of vector address manually

                data_s             <= (others => '0');

                data_s(1 downto 0) <= "11";

                if tim_int_s then

                  data_s(2)        <= '1';