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[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] [verif/] [black_box/] [rb/] [int/] [test.asm] - Blame information for rev 12

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        ;; *******************************************************************
        ;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
        ;;
        ;; Test interrupts in conjunction with RB-switching.
        ;; *******************************************************************
 
        INCLUDE "cpu.inc"
        INCLUDE "pass_fail.inc"
 
        ORG     0
 
        jmp     start
        nop
        jmp     interrupt
        jmp     fail
        jmp     fail
        jmp     fail
 
 
        ;; Start of test
start:
        ;; fill RB0
        clr     a
        call    fill
 
        ;; fill RB1
        sel     rb1
        mov     a, #010H
        call    fill
        sel     rb0
 
        ;; set up interrupt
        clr     f1
        ;; sync on next interrupt
        call    sync_on_int
 
        mov     r0, #000H
        en      i
loop1:  jf1     goon1
        djnz    r0, loop1
        jmp     fail
 
goon1:
        dis     i
        clr     f1
 
        ;; check BS implicitely
        ;; r0 must not be zero
        mov     a, r0
        jz      fail
 
        ;; check RB1
        sel     rb1
        call    check_0
 
        ;; check RB0
        sel     rb0
        call    check_rb0
 
pass:   PASS
 
fail:   FAIL
 
 
        ORG     0200H
interrupt:
        sel     rb1
        mov     r0, a
 
        call    check_rb1
 
        clr     a
        mov     r1, a
        mov     r2, a
        mov     r3, a
        mov     r4, a
        mov     r5, a
        mov     r6, a
        mov     r7, a
        xch     a, r0
 
        cpl     f1
 
        retr
 
 
        ORG     0300H
 
fill:   add     a, #0B0H
        mov     r0, a
        inc     a
        mov     r1, a
        inc     a
        mov     r2, a
        inc     a
        mov     r3, a
        inc     a
        mov     r4, a
        inc     a
        mov     r5, a
        inc     a
        mov     r6, a
        inc     a
        mov     r7, a
        ret
 
check_0:
        mov     a, r0
        jnz     fail_p3
        mov     a, r1
        jnz     fail_p3
        mov     a, r2
        jnz     fail_p3
        mov     a, r3
        jnz     fail_p3
        mov     a, r4
        jnz     fail_p3
        mov     a, r5
        jnz     fail_p3
        mov     a, r6
        jnz     fail_p3
        mov     a, r7
        jnz     fail_p3
        ret
 
sync_on_int:
        jni     wait_int2
        jmp     sync_on_int
 
wait_int2:
        jni     wait_int2
        call    clr_int
        retr
 
clr_int:
        ;; clear latched interrupt request with RETR!
        retr
 
check_rb1:
        mov     a, #(~0C1H & 0FFH)
        add     a, r1
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C2H & 0FFH)
        add     a, r2
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C3H & 0FFH)
        add     a, r3
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C4H & 0FFH)
        add     a, r4
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C5H & 0FFH)
        add     a, r5
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C6H & 0FFH)
        add     a, r6
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0C7H & 0FFH)
        add     a, r7
        cpl     a
        jnz     fail_p3
 
        ret
 
check_rb0:
        mov     a, #(~0B1H & 0FFH)
        add     a, r1
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B2H & 0FFH)
        add     a, r2
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B3H & 0FFH)
        add     a, r3
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B4H & 0FFH)
        add     a, r4
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B5H & 0FFH)
        add     a, r5
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B6H & 0FFH)
        add     a, r6
        cpl     a
        jnz     fail_p3
 
        mov     a, #(~0B7H & 0FFH)
        add     a, r7
        cpl     a
        jnz     fail_p3
 
        ret
 
fail_p3:
        FAIL

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[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] [verif/] [black_box/] [rb/] [int/] [test.asm] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	arniml	`;; *******************************************************************`
2			`;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $`
3			`;;`
4			`;; Test interrupts in conjunction with RB-switching.`
5			`;; *******************************************************************`
6
7			`INCLUDE "cpu.inc"`
8			`INCLUDE "pass_fail.inc"`
9
10			`ORG 0`
11
12			`jmp start`
13			`nop`
14			`jmp interrupt`
15			`jmp fail`
16			`jmp fail`
17			`jmp fail`
18
19
20			`;; Start of test`
21			`start:`
22			`;; fill RB0`
23			`clr a`
24			`call fill`
25
26			`;; fill RB1`
27			`sel rb1`
28			`mov a, #010H`
29			`call fill`
30			`sel rb0`
31
32			`;; set up interrupt`
33			`clr f1`
34			`;; sync on next interrupt`
35			`call sync_on_int`
36
37			`mov r0, #000H`
38			`en i`
39			`loop1: jf1 goon1`
40			`djnz r0, loop1`
41			`jmp fail`
42
43			`goon1:`
44			`dis i`
45			`clr f1`
46
47			`;; check BS implicitely`
48			`;; r0 must not be zero`
49			`mov a, r0`
50			`jz fail`
51
52			`;; check RB1`
53			`sel rb1`
54			`call check_0`
55
56			`;; check RB0`
57			`sel rb0`
58			`call check_rb0`
59
60			`pass: PASS`
61
62			`fail: FAIL`
63
64
65			`ORG 0200H`
66			`interrupt:`
67			`sel rb1`
68			`mov r0, a`
69
70			`call check_rb1`
71
72			`clr a`
73			`mov r1, a`
74			`mov r2, a`
75			`mov r3, a`
76			`mov r4, a`
77			`mov r5, a`
78			`mov r6, a`
79			`mov r7, a`
80			`xch a, r0`
81
82			`cpl f1`
83
84			`retr`
85
86
87			`ORG 0300H`
88
89			`fill: add a, #0B0H`
90			`mov r0, a`
91			`inc a`
92			`mov r1, a`
93			`inc a`
94			`mov r2, a`
95			`inc a`
96			`mov r3, a`
97			`inc a`
98			`mov r4, a`
99			`inc a`
100			`mov r5, a`
101			`inc a`
102			`mov r6, a`
103			`inc a`
104			`mov r7, a`
105			`ret`
106
107			`check_0:`
108			`mov a, r0`
109			`jnz fail_p3`
110			`mov a, r1`
111			`jnz fail_p3`
112			`mov a, r2`
113			`jnz fail_p3`
114			`mov a, r3`
115			`jnz fail_p3`
116			`mov a, r4`
117			`jnz fail_p3`
118			`mov a, r5`
119			`jnz fail_p3`
120			`mov a, r6`
121			`jnz fail_p3`
122			`mov a, r7`
123			`jnz fail_p3`
124			`ret`
125
126			`sync_on_int:`
127			`jni wait_int2`
128			`jmp sync_on_int`
129
130			`wait_int2:`
131			`jni wait_int2`
132			`call clr_int`
133			`retr`
134
135			`clr_int:`
136			`;; clear latched interrupt request with RETR!`
137			`retr`
138
139			`check_rb1:`
140			`mov a, #(~0C1H & 0FFH)`
141			`add a, r1`
142			`cpl a`
143			`jnz fail_p3`
144
145			`mov a, #(~0C2H & 0FFH)`
146			`add a, r2`
147			`cpl a`
148			`jnz fail_p3`
149
150			`mov a, #(~0C3H & 0FFH)`
151			`add a, r3`
152			`cpl a`
153			`jnz fail_p3`
154
155			`mov a, #(~0C4H & 0FFH)`
156			`add a, r4`
157			`cpl a`
158			`jnz fail_p3`
159
160			`mov a, #(~0C5H & 0FFH)`
161			`add a, r5`
162			`cpl a`
163			`jnz fail_p3`
164
165			`mov a, #(~0C6H & 0FFH)`
166			`add a, r6`
167			`cpl a`
168			`jnz fail_p3`
169
170			`mov a, #(~0C7H & 0FFH)`
171			`add a, r7`
172			`cpl a`
173			`jnz fail_p3`
174
175			`ret`
176
177			`check_rb0:`
178			`mov a, #(~0B1H & 0FFH)`
179			`add a, r1`
180			`cpl a`
181			`jnz fail_p3`
182
183			`mov a, #(~0B2H & 0FFH)`
184			`add a, r2`
185			`cpl a`
186			`jnz fail_p3`
187
188			`mov a, #(~0B3H & 0FFH)`
189			`add a, r3`
190			`cpl a`
191			`jnz fail_p3`
192
193			`mov a, #(~0B4H & 0FFH)`
194			`add a, r4`
195			`cpl a`
196			`jnz fail_p3`
197
198			`mov a, #(~0B5H & 0FFH)`
199			`add a, r5`
200			`cpl a`
201			`jnz fail_p3`
202
203			`mov a, #(~0B6H & 0FFH)`
204			`add a, r6`
205			`cpl a`
206			`jnz fail_p3`
207
208			`mov a, #(~0B7H & 0FFH)`
209			`add a, r7`
210			`cpl a`
211			`jnz fail_p3`
212
213			`ret`
214
215			`fail_p3:`
216			`FAIL`