1 |
4 |
arniml |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- The BUS unit.
|
4 |
|
|
-- Implements the BUS port logic.
|
5 |
|
|
--
|
6 |
|
|
-- $Id: db_bus.vhd,v 1.1 2004-03-23 21:31:52 arniml Exp $
|
7 |
|
|
--
|
8 |
|
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
9 |
|
|
--
|
10 |
|
|
-- All rights reserved
|
11 |
|
|
--
|
12 |
|
|
-- Redistribution and use in source and synthezised forms, with or without
|
13 |
|
|
-- modification, are permitted provided that the following conditions are met:
|
14 |
|
|
--
|
15 |
|
|
-- Redistributions of source code must retain the above copyright notice,
|
16 |
|
|
-- this list of conditions and the following disclaimer.
|
17 |
|
|
--
|
18 |
|
|
-- Redistributions in synthesized form must reproduce the above copyright
|
19 |
|
|
-- notice, this list of conditions and the following disclaimer in the
|
20 |
|
|
-- documentation and/or other materials provided with the distribution.
|
21 |
|
|
--
|
22 |
|
|
-- Neither the name of the author nor the names of other contributors may
|
23 |
|
|
-- be used to endorse or promote products derived from this software without
|
24 |
|
|
-- specific prior written permission.
|
25 |
|
|
--
|
26 |
|
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
27 |
|
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
28 |
|
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
29 |
|
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
30 |
|
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
31 |
|
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
32 |
|
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
33 |
|
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
34 |
|
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
35 |
|
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
36 |
|
|
-- POSSIBILITY OF SUCH DAMAGE.
|
37 |
|
|
--
|
38 |
|
|
-- Please report bugs to the author, but before you do so, please
|
39 |
|
|
-- make sure that this is not a derivative work and that
|
40 |
|
|
-- you have the latest version of this file.
|
41 |
|
|
--
|
42 |
|
|
-- The latest version of this file can be found at:
|
43 |
|
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
44 |
|
|
--
|
45 |
|
|
-------------------------------------------------------------------------------
|
46 |
|
|
|
47 |
|
|
library ieee;
|
48 |
|
|
use ieee.std_logic_1164.all;
|
49 |
|
|
|
50 |
|
|
use work.t48_pack.word_t;
|
51 |
|
|
|
52 |
|
|
entity db_bus is
|
53 |
|
|
|
54 |
|
|
port (
|
55 |
|
|
-- Global Interface -------------------------------------------------------
|
56 |
|
|
clk_i : in std_logic;
|
57 |
|
|
res_i : in std_logic;
|
58 |
|
|
en_clk_i : in boolean;
|
59 |
|
|
ea_i : in std_logic;
|
60 |
|
|
-- T48 Bus Interface ------------------------------------------------------
|
61 |
|
|
data_i : in word_t;
|
62 |
|
|
data_o : out word_t;
|
63 |
|
|
write_bus_i : in boolean;
|
64 |
|
|
read_bus_i : in boolean;
|
65 |
|
|
-- BUS Interface ----------------------------------------------------------
|
66 |
|
|
output_pcl_i : in boolean;
|
67 |
|
|
bidir_bus_i : in boolean;
|
68 |
|
|
pcl_i : in word_t;
|
69 |
|
|
db_i : in word_t;
|
70 |
|
|
db_o : out word_t;
|
71 |
|
|
db_dir_o : out std_logic
|
72 |
|
|
);
|
73 |
|
|
|
74 |
|
|
end db_bus;
|
75 |
|
|
|
76 |
|
|
|
77 |
|
|
use work.t48_pack.clk_active_c;
|
78 |
|
|
use work.t48_pack.res_active_c;
|
79 |
|
|
use work.t48_pack.bus_idle_level_c;
|
80 |
|
|
use work.t48_pack.to_stdLogic;
|
81 |
|
|
|
82 |
|
|
architecture rtl of db_bus is
|
83 |
|
|
|
84 |
|
|
-- the BUS output register
|
85 |
|
|
signal bus_q : word_t;
|
86 |
|
|
|
87 |
|
|
-- BUS direction marker
|
88 |
|
|
signal db_dir_q : std_logic;
|
89 |
|
|
|
90 |
|
|
begin
|
91 |
|
|
|
92 |
|
|
-----------------------------------------------------------------------------
|
93 |
|
|
-- Process bus_regs
|
94 |
|
|
--
|
95 |
|
|
-- Purpose:
|
96 |
|
|
-- Implements the BUS output register.
|
97 |
|
|
--
|
98 |
|
|
bus_regs: process (res_i, clk_i)
|
99 |
|
|
begin
|
100 |
|
|
if res_i = res_active_c then
|
101 |
|
|
bus_q <= (others => '1');
|
102 |
|
|
db_dir_q <= '0';
|
103 |
|
|
|
104 |
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
105 |
|
|
if en_clk_i then
|
106 |
|
|
|
107 |
|
|
if write_bus_i then
|
108 |
|
|
bus_q <= data_i;
|
109 |
|
|
|
110 |
|
|
db_dir_q <= '1';
|
111 |
|
|
|
112 |
|
|
elsif ea_i = '1' or bidir_bus_i then
|
113 |
|
|
db_dir_q <= '0';
|
114 |
|
|
|
115 |
|
|
end if;
|
116 |
|
|
|
117 |
|
|
end if;
|
118 |
|
|
|
119 |
|
|
end if;
|
120 |
|
|
|
121 |
|
|
end process bus_regs;
|
122 |
|
|
--
|
123 |
|
|
-----------------------------------------------------------------------------
|
124 |
|
|
|
125 |
|
|
|
126 |
|
|
-----------------------------------------------------------------------------
|
127 |
|
|
-- Output Mapping.
|
128 |
|
|
-----------------------------------------------------------------------------
|
129 |
|
|
db_o <= pcl_i
|
130 |
|
|
when output_pcl_i else
|
131 |
|
|
bus_q;
|
132 |
|
|
db_dir_o <= db_dir_q or to_stdLogic(output_pcl_i);
|
133 |
|
|
data_o <= (others => bus_idle_level_c)
|
134 |
|
|
when not read_bus_i else
|
135 |
|
|
db_i;
|
136 |
|
|
|
137 |
|
|
end rtl;
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
-------------------------------------------------------------------------------
|
141 |
|
|
-- File History:
|
142 |
|
|
--
|
143 |
|
|
-- $Log: not supported by cvs2svn $
|
144 |
|
|
--
|
145 |
|
|
-------------------------------------------------------------------------------
|