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[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] [vhdl/] [t48_core_comp_pack-p.vhd] - Blame information for rev 292

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-------------------------------------------------------------------------------
--
-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package t48_core_comp_pack is
 
  component t48_core
    generic (
      xtal_div_3_g          : integer := 1;
      register_mnemonic_g   : integer := 1;
      include_port1_g       : integer := 1;
      include_port2_g       : integer := 1;
      include_bus_g         : integer := 1;
      include_timer_g       : integer := 1;
      sample_t1_state_g     : integer := 4
    );
 
    port (
      xtal_i       : in  std_logic;
      reset_i      : in  std_logic;
      t0_i         : in  std_logic;
      t0_o         : out std_logic;
      t0_dir_o     : out std_logic;
      int_n_i      : in  std_logic;
      ea_i         : in  std_logic;
      rd_n_o       : out std_logic;
      psen_n_o     : out std_logic;
      wr_n_o       : out std_logic;
      ale_o        : out std_logic;
      db_i         : in  std_logic_vector( 7 downto 0);
      db_o         : out std_logic_vector( 7 downto 0);
      db_dir_o     : out std_logic;
      t1_i         : in  std_logic;
      p2_i         : in  std_logic_vector( 7 downto 0);
      p2_o         : out std_logic_vector( 7 downto 0);
      p2_low_imp_o : out std_logic;
      p1_i         : in  std_logic_vector( 7 downto 0);
      p1_o         : out std_logic_vector( 7 downto 0);
      p1_low_imp_o : out std_logic;
      prog_n_o     : out std_logic;
      clk_i        : in  std_logic;
      en_clk_i     : in  std_logic;
      xtal3_o      : out std_logic;
      dmem_addr_o  : out std_logic_vector( 7 downto 0);
      dmem_we_o    : out std_logic;
      dmem_data_i  : in  std_logic_vector( 7 downto 0);
      dmem_data_o  : out std_logic_vector( 7 downto 0);
      pmem_addr_o  : out std_logic_vector(11 downto 0);
      pmem_data_i  : in  std_logic_vector( 7 downto 0)
    );
  end component;
 
  component syn_rom
    generic (
      address_width_g : positive := 10
    );
    port (
      clk_i      : in  std_logic;
      rom_addr_i : in  std_logic_vector(address_width_g-1 downto 0);
      rom_data_o : out std_logic_vector(7 downto 0)
    );
  end component;
 
  component syn_ram
    generic (
      address_width_g : positive := 8
    );
    port (
      clk_i      : in  std_logic;
      res_i      : in  std_logic;
      ram_addr_i : in  std_logic_vector(address_width_g-1 downto 0);
      ram_data_i : in  std_logic_vector(7 downto 0);
      ram_we_i   : in  std_logic;
      ram_data_o : out std_logic_vector(7 downto 0)
    );
  end component;
 
end t48_core_comp_pack;

Line No.	Rev	Author	Line
1	4	arniml	`-------------------------------------------------------------------------------`
2			`--`
3	32	arniml	`-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $`
4	4	arniml	`--`
5			`-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)`
6			`--`
7			`-- All rights reserved`
8			`--`
9			`-------------------------------------------------------------------------------`
10
11			`library ieee;`
12			`use ieee.std_logic_1164.all;`
13
14			`package t48_core_comp_pack is`
15
16			`component t48_core`
17			`generic (`
18			`xtal_div_3_g : integer := 1;`
19			`register_mnemonic_g : integer := 1;`
20			`include_port1_g : integer := 1;`
21			`include_port2_g : integer := 1;`
22			`include_bus_g : integer := 1;`
23			`include_timer_g : integer := 1;`
24			`sample_t1_state_g : integer := 4`
25			`);`
26
27			`port (`
28	32	arniml	`xtal_i : in std_logic;`
29			`reset_i : in std_logic;`
30			`t0_i : in std_logic;`
31			`t0_o : out std_logic;`
32			`t0_dir_o : out std_logic;`
33			`int_n_i : in std_logic;`
34			`ea_i : in std_logic;`
35			`rd_n_o : out std_logic;`
36			`psen_n_o : out std_logic;`
37			`wr_n_o : out std_logic;`
38			`ale_o : out std_logic;`
39			`db_i : in std_logic_vector( 7 downto 0);`
40			`db_o : out std_logic_vector( 7 downto 0);`
41			`db_dir_o : out std_logic;`
42			`t1_i : in std_logic;`
43			`p2_i : in std_logic_vector( 7 downto 0);`
44			`p2_o : out std_logic_vector( 7 downto 0);`
45			`p2_low_imp_o : out std_logic;`
46			`p1_i : in std_logic_vector( 7 downto 0);`
47			`p1_o : out std_logic_vector( 7 downto 0);`
48			`p1_low_imp_o : out std_logic;`
49			`prog_n_o : out std_logic;`
50			`clk_i : in std_logic;`
51			`en_clk_i : in std_logic;`
52			`xtal3_o : out std_logic;`
53			`dmem_addr_o : out std_logic_vector( 7 downto 0);`
54			`dmem_we_o : out std_logic;`
55			`dmem_data_i : in std_logic_vector( 7 downto 0);`
56			`dmem_data_o : out std_logic_vector( 7 downto 0);`
57			`pmem_addr_o : out std_logic_vector(11 downto 0);`
58			`pmem_data_i : in std_logic_vector( 7 downto 0)`
59	4	arniml	`);`
60			`end component;`
61
62			`component syn_rom`
63			`generic (`
64			`address_width_g : positive := 10`
65			`);`
66			`port (`
67			`clk_i : in std_logic;`
68			`rom_addr_i : in std_logic_vector(address_width_g-1 downto 0);`
69			`rom_data_o : out std_logic_vector(7 downto 0)`
70			`);`
71			`end component;`
72
73			`component syn_ram`
74			`generic (`
75			`address_width_g : positive := 8`
76			`);`
77			`port (`
78			`clk_i : in std_logic;`
79			`res_i : in std_logic;`
80			`ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);`
81			`ram_data_i : in std_logic_vector(7 downto 0);`
82			`ram_we_i : in std_logic;`
83			`ram_data_o : out std_logic_vector(7 downto 0)`
84			`);`
85			`end component;`
86
87			`end t48_core_comp_pack;`

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[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] [vhdl/] [t48_core_comp_pack-p.vhd] - Blame information for rev 292