OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] [verif/] [black_box/] [xrl/] [rr/] [test.asm] - Blame information for rev 292

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 arniml
        ;; *******************************************************************
2
        ;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
3
        ;;
4
        ;; Test XRL A, Rr for RB0 and RB1
5
        ;; *******************************************************************
6
 
7
        INCLUDE "cpu.inc"
8
        INCLUDE "pass_fail.inc"
9
 
10
        ORG     0
11
 
12
        ;; Start of test
13
 
14
        ;; fill RB0
15
        call    fill
16
 
17
        ;; check RB0
18
        call    check
19
 
20
        ;; fill RB1
21
        sel     rb1
22
        call    fill
23
        sel     rb0
24
 
25
        ;; clear RB0
26
        call    clr_rb0
27
 
28
        ;; check RB1
29
        sel     rb1
30
        call    check
31
 
32
        ;; check RB0 for all 0
33
        mov     r0, #000H
34
        mov     r1, #008H
35
chk0_loop:
36
        mov     a, @r0
37
        jnz     fail
38
        inc     r0
39
        djnz    r1, chk0_loop
40
 
41
pass:   PASS
42
 
43
fail:   FAIL
44
 
45
 
46
        ORG     0300H
47
 
48
fill:   mov     a, #0FEH
49
        mov     r0, a
50
        mov     a, #0FDH
51
        mov     r1, a
52
        mov     a, #0FBH
53
        mov     r2, a
54
        mov     a, #0F7H
55
        mov     r3, a
56
        mov     a, #0EFH
57
        mov     r4, a
58
        mov     a, #0DFH
59
        mov     r5, a
60
        mov     a, #0BFH
61
        mov     r6, a
62
        mov     a, #07FH
63
        mov     r7, a
64
        ret
65
 
66
clr_rb0:
67
        mov     r0, #007H
68
        clr     a
69
clr_loop:
70
        mov     @r0, a
71
        djnz    r0, clr_loop
72
        ret
73
 
74
check:  mov     a, #(1 << 0)
75
        xrl     a, r0
76
        cpl     a
77
        jnz     fail_p3
78
        dec     a
79
        xrl     a, r0
80
        cpl     a
81
        add     a, #(~(0FFH - (1 << 0)) + 1) & 0FFH
82
        jnz     fail_p3
83
 
84
        mov     a, #(1 << 1)
85
        xrl     a, r1
86
        cpl     a
87
        jnz     fail_p3
88
        dec     a
89
        xrl     a, r1
90
        cpl     a
91
        add     a, #(~(0FFH - (1 << 1)) + 1) & 0FFH
92
        jnz     fail_p3
93
 
94
        mov     a, #(1 << 2)
95
        xrl     a, r2
96
        cpl     a
97
        jnz     fail_p3
98
        dec     a
99
        xrl     a, r2
100
        cpl     a
101
        add     a, #(~(0FFH - (1 << 2)) + 1) & 0FFH
102
        jnz     fail_p3
103
 
104
        mov     a, #(1 << 3)
105
        xrl     a, r3
106
        cpl     a
107
        jnz     fail_p3
108
        dec     a
109
        xrl     a, r3
110
        cpl     a
111
        add     a, #(~(0FFH - (1 << 3)) + 1) & 0FFH
112
        jnz     fail_p3
113
 
114
        mov     a, #(1 << 4)
115
        xrl     a, r4
116
        cpl     a
117
        jnz     fail_p3
118
        dec     a
119
        xrl     a, r4
120
        cpl     a
121
        add     a, #(~(0FFH - (1 << 4)) + 1) & 0FFH
122
        jnz     fail_p3
123
 
124
        mov     a, #(1 << 5)
125
        xrl     a, r5
126
        cpl     a
127
        jnz     fail_p3
128
        dec     a
129
        xrl     a, r5
130
        cpl     a
131
        add     a, #(~(0FFH - (1 << 5)) + 1) & 0FFH
132
        jnz     fail_p3
133
 
134
        mov     a, #(1 << 6)
135
        xrl     a, r6
136
        cpl     a
137
        jnz     fail_p3
138
        dec     a
139
        xrl     a, r6
140
        cpl     a
141
        add     a, #(~(0FFH - (1 << 6)) + 1) & 0FFH
142
        jnz     fail_p3
143
 
144
        mov     a, #(1 << 7)
145
        xrl     a, r7
146
        cpl     a
147
        jnz     fail_p3
148
        dec     a
149
        xrl     a, r7
150
        cpl     a
151
        add     a, #(~(0FFH - (1 << 7)) + 1) & 0FFH
152
        jnz     fail_p3
153
 
154
        ret
155
 
156
fail_p3:
157
        FAIL

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.