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arniml |
-------------------------------------------------------------------------------
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--
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-- The Opcode Decoder.
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-- Derives instruction mnemonics and multicycle information
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-- using the OPC table unit.
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--
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arniml |
-- $Id: opc_decoder.vhd,v 1.2 2004-07-11 16:51:33 arniml Exp $
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arniml |
--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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use work.decoder_pack.mnemonic_t;
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entity opc_decoder is
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generic (
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-- store mnemonic in flip-flops (registered-out)
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register_mnemonic_g : integer := 1
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);
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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read_bus_i : in boolean;
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-- Decoder Interface ------------------------------------------------------
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inj_int_i : in boolean;
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opcode_o : out word_t;
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mnemonic_o : out mnemonic_t;
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multi_cycle_o : out boolean
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);
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end opc_decoder;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.to_boolean;
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--use work.decoder_pack.MN_NOP;
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use work.decoder_pack.all;
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use work.t48_comp_pack.opc_table;
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architecture rtl of opc_decoder is
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-- the opcode register
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signal opcode_q : word_t;
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-- the mnemonic
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signal mnemonic_s,
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mnemonic_q : mnemonic_t;
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signal multi_cycle_s : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Verify the generics
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-----------------------------------------------------------------------------
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-- pragma translate_off
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-- Register Mnemonic --------------------------------------------------------
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assert (register_mnemonic_g = 1) or (register_mnemonic_g = 0)
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report "register_mnemonic_g must be either 1 or 0!"
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severity failure;
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-- pragma translate_on
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-----------------------------------------------------------------------------
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-- Opcode Decoder Table
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-----------------------------------------------------------------------------
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opc_table_b : opc_table
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port map (
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opcode_i => opcode_q,
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multi_cycle_o => multi_cycle_s,
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mnemonic_o => mnemonic_s
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);
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-----------------------------------------------------------------------------
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-- Process regs
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--
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-- Purpose:
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-- Implements the opcode and mnemonic registers.
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--
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regs: process (res_i, clk_i)
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begin
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if res_i = res_active_c then
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opcode_q <= (others => '0'); -- NOP
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mnemonic_q <= MN_NOP;
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if read_bus_i then
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opcode_q <= data_i;
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elsif inj_int_i then
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opcode_q <= "00010100";
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else
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mnemonic_q <= mnemonic_s;
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end if;
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end if;
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end if;
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end process regs;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping.
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-----------------------------------------------------------------------------
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opcode_o <= opcode_q;
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multi_cycle_o <= to_boolean(multi_cycle_s);
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mnemonic_o <= mnemonic_q
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when register_mnemonic_g = 1 else
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mnemonic_s;
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end rtl;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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--
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--
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arniml |
-------------------------------------------------------------------------------
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