1 |
4 |
arniml |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- The Program Status Word (PSW).
|
4 |
|
|
-- Implements the PSW with its special bits.
|
5 |
|
|
--
|
6 |
|
|
-- $Id: psw.vhd,v 1.1 2004-03-23 21:31:53 arniml Exp $
|
7 |
|
|
--
|
8 |
|
|
-- All rights reserved
|
9 |
|
|
--
|
10 |
|
|
-- Redistribution and use in source and synthezised forms, with or without
|
11 |
|
|
-- modification, are permitted provided that the following conditions are met:
|
12 |
|
|
--
|
13 |
|
|
-- Redistributions of source code must retain the above copyright notice,
|
14 |
|
|
-- this list of conditions and the following disclaimer.
|
15 |
|
|
--
|
16 |
|
|
-- Redistributions in synthesized form must reproduce the above copyright
|
17 |
|
|
-- notice, this list of conditions and the following disclaimer in the
|
18 |
|
|
-- documentation and/or other materials provided with the distribution.
|
19 |
|
|
--
|
20 |
|
|
-- Neither the name of the author nor the names of other contributors may
|
21 |
|
|
-- be used to endorse or promote products derived from this software without
|
22 |
|
|
-- specific prior written permission.
|
23 |
|
|
--
|
24 |
|
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
25 |
|
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
26 |
|
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
27 |
|
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
28 |
|
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
29 |
|
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
30 |
|
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
31 |
|
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
32 |
|
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
33 |
|
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
34 |
|
|
-- POSSIBILITY OF SUCH DAMAGE.
|
35 |
|
|
--
|
36 |
|
|
-- Please report bugs to the author, but before you do so, please
|
37 |
|
|
-- make sure that this is not a derivative work and that
|
38 |
|
|
-- you have the latest version of this file.
|
39 |
|
|
--
|
40 |
|
|
-- The latest version of this file can be found at:
|
41 |
|
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
42 |
|
|
--
|
43 |
|
|
-------------------------------------------------------------------------------
|
44 |
|
|
|
45 |
|
|
library ieee;
|
46 |
|
|
use ieee.std_logic_1164.all;
|
47 |
|
|
|
48 |
|
|
use work.t48_pack.word_t;
|
49 |
|
|
|
50 |
|
|
entity psw is
|
51 |
|
|
|
52 |
|
|
port (
|
53 |
|
|
-- Global Interface -------------------------------------------------------
|
54 |
|
|
clk_i : in std_logic;
|
55 |
|
|
res_i : in std_logic;
|
56 |
|
|
en_clk_i : in boolean;
|
57 |
|
|
-- T48 Bus Interface ------------------------------------------------------
|
58 |
|
|
data_i : in word_t;
|
59 |
|
|
data_o : out word_t;
|
60 |
|
|
read_psw_i : in boolean;
|
61 |
|
|
read_sp_i : in boolean;
|
62 |
|
|
write_psw_i : in boolean;
|
63 |
|
|
write_sp_i : in boolean;
|
64 |
|
|
-- Decoder Interface ------------------------------------------------------
|
65 |
|
|
special_data_i : in std_logic;
|
66 |
|
|
inc_stackp_i : in boolean;
|
67 |
|
|
dec_stackp_i : in boolean;
|
68 |
|
|
write_carry_i : in boolean;
|
69 |
|
|
write_aux_carry_i : in boolean;
|
70 |
|
|
write_f0_i : in boolean;
|
71 |
|
|
write_bs_i : in boolean;
|
72 |
|
|
carry_o : out std_logic;
|
73 |
|
|
aux_carry_o : out std_logic;
|
74 |
|
|
f0_o : out std_logic;
|
75 |
|
|
bs_o : out std_logic
|
76 |
|
|
);
|
77 |
|
|
|
78 |
|
|
end psw;
|
79 |
|
|
|
80 |
|
|
|
81 |
|
|
library ieee;
|
82 |
|
|
use ieee.std_logic_arith.all;
|
83 |
|
|
|
84 |
|
|
use work.t48_pack.clk_active_c;
|
85 |
|
|
use work.t48_pack.res_active_c;
|
86 |
|
|
use work.t48_pack.bus_idle_level_c;
|
87 |
|
|
|
88 |
|
|
architecture rtl of psw is
|
89 |
|
|
|
90 |
|
|
-- special bit positions in PSW
|
91 |
|
|
constant carry_c : natural := 3;
|
92 |
|
|
constant aux_carry_c : natural := 2;
|
93 |
|
|
constant f0_c : natural := 1;
|
94 |
|
|
constant bs_c : natural := 0;
|
95 |
|
|
|
96 |
|
|
-- the PSW register
|
97 |
|
|
signal psw_q : std_logic_vector(3 downto 0);
|
98 |
|
|
-- the Stack Pointer
|
99 |
|
|
signal sp_q : unsigned(2 downto 0);
|
100 |
|
|
|
101 |
|
|
begin
|
102 |
|
|
|
103 |
|
|
-----------------------------------------------------------------------------
|
104 |
|
|
-- Process psw_reg
|
105 |
|
|
--
|
106 |
|
|
-- Purpose:
|
107 |
|
|
-- Implements the PSW register.
|
108 |
|
|
--
|
109 |
|
|
psw_reg: process (res_i, clk_i)
|
110 |
|
|
begin
|
111 |
|
|
if res_i = res_active_c then
|
112 |
|
|
psw_q <= (others => '0');
|
113 |
|
|
sp_q <= (others => '0');
|
114 |
|
|
|
115 |
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
116 |
|
|
if en_clk_i then
|
117 |
|
|
|
118 |
|
|
-- T48 bus access
|
119 |
|
|
if write_psw_i then
|
120 |
|
|
psw_q <= data_i(7 downto 4);
|
121 |
|
|
end if;
|
122 |
|
|
if write_sp_i then
|
123 |
|
|
sp_q <= unsigned(data_i(2 downto 0));
|
124 |
|
|
end if;
|
125 |
|
|
|
126 |
|
|
-- increment Stack Pointer
|
127 |
|
|
if inc_stackp_i then
|
128 |
|
|
sp_q <= sp_q + 1;
|
129 |
|
|
end if;
|
130 |
|
|
-- decrement Stack Pointer
|
131 |
|
|
if dec_stackp_i then
|
132 |
|
|
sp_q <= sp_q - 1;
|
133 |
|
|
end if;
|
134 |
|
|
|
135 |
|
|
-- access to special bits
|
136 |
|
|
if write_carry_i then
|
137 |
|
|
psw_q(carry_c) <= special_data_i;
|
138 |
|
|
end if;
|
139 |
|
|
--
|
140 |
|
|
if write_aux_carry_i then
|
141 |
|
|
psw_q(aux_carry_c) <= special_data_i;
|
142 |
|
|
end if;
|
143 |
|
|
--
|
144 |
|
|
if write_f0_i then
|
145 |
|
|
psw_q(f0_c) <= special_data_i;
|
146 |
|
|
end if;
|
147 |
|
|
--
|
148 |
|
|
if write_bs_i then
|
149 |
|
|
psw_q(bs_c) <= special_data_i;
|
150 |
|
|
end if;
|
151 |
|
|
|
152 |
|
|
end if;
|
153 |
|
|
|
154 |
|
|
end if;
|
155 |
|
|
|
156 |
|
|
end process psw_reg;
|
157 |
|
|
--
|
158 |
|
|
-----------------------------------------------------------------------------
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
-----------------------------------------------------------------------------
|
162 |
|
|
-- Process data_out
|
163 |
|
|
--
|
164 |
|
|
-- Purpose:
|
165 |
|
|
-- Output multiplexer for T48 Data Bus.
|
166 |
|
|
--
|
167 |
|
|
data_out: process (read_psw_i,
|
168 |
|
|
read_sp_i,
|
169 |
|
|
psw_q,
|
170 |
|
|
sp_q)
|
171 |
|
|
begin
|
172 |
|
|
data_o <= (others => bus_idle_level_c);
|
173 |
|
|
|
174 |
|
|
if read_psw_i then
|
175 |
|
|
data_o(7 downto 4) <= psw_q;
|
176 |
|
|
end if;
|
177 |
|
|
|
178 |
|
|
if read_sp_i then
|
179 |
|
|
data_o(3 downto 0) <= '1' & conv_std_logic_vector(sp_q, 3);
|
180 |
|
|
end if;
|
181 |
|
|
|
182 |
|
|
end process data_out;
|
183 |
|
|
--
|
184 |
|
|
-----------------------------------------------------------------------------
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
-----------------------------------------------------------------------------
|
188 |
|
|
-- Output mapping.
|
189 |
|
|
-----------------------------------------------------------------------------
|
190 |
|
|
carry_o <= psw_q(carry_c);
|
191 |
|
|
aux_carry_o <= psw_q(aux_carry_c);
|
192 |
|
|
f0_o <= psw_q(f0_c);
|
193 |
|
|
bs_o <= psw_q(bs_c);
|
194 |
|
|
|
195 |
|
|
end rtl;
|
196 |
|
|
|
197 |
|
|
|
198 |
|
|
-------------------------------------------------------------------------------
|
199 |
|
|
-- File History:
|
200 |
|
|
--
|
201 |
|
|
-- $Log: not supported by cvs2svn $
|
202 |
|
|
--
|
203 |
|
|
-------------------------------------------------------------------------------
|