OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [KNOWN_BUGS] - Blame information for rev 109

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 105 arniml
 
2
Known bugs of the T48 uController core
3
======================================
4 109 arniml
Version: $Date: 2004-05-20 22:00:59 $
5 105 arniml
 
6
 
7
Release 0.1 BETA
8
----------------
9
 
10
******************************************************************************
11 109 arniml
External Program Memory ignored when EA = 0
12
 
13
The external Program Memory is always ignored when EA = 0 with the t8048 system
14
toplevel. Desired behaviour is to access external Program Memory when code
15
has to be fetched from an address location that is outside the internal
16
Program Memory.
17
 
18
Fixed in t8048.vhd 1.3
19
Fix will be included in next release.
20
 
21
******************************************************************************
22 105 arniml
ANL and ORL to P2 read port status instead of port output register
23
 
24
The ANL and ORL instructions for P2 read the port status and apply the logical
25
operation on this value. Instead, they should read the port output register
26
and operate on this value.
27
 
28
Fixed in p2.vhd 1.5
29
Regression test:
30
white_box/p2_port_reg_conflict
31
Fix will be included in next release.
32
 
33
******************************************************************************
34
Counter is not incremented
35
 
36
When in counter mode, the timer/counter module does not increment upon a
37
falling edge of T1. Reason is a typo in the code for the edge detection signal
38
t1_inc_s - it will never become true.
39
 
40
Fixed in timer.vhd 1.3
41
Regression tests:
42
black_box/cnt/cnt
43
black_box/cnt/int
44
Fix will be included in next release.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.