OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [t48_system_comp_pack-p.vhd] - Blame information for rev 165

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 148 arniml 
-------------------------------------------------------------------------------
2 
--
3 165 arniml 
-- $Id: t48_system_comp_pack-p.vhd,v 1.4 2005-05-05 19:49:58 arniml Exp $
4 148 arniml 
--
5 
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
6 
--
7 
-- All rights reserved
8 
--
9 
-------------------------------------------------------------------------------
10 
 
11 
library ieee;
12 
use ieee.std_logic_1164.all;
13 
 
14 
package t48_system_comp_pack is
15 
 
16 165 arniml 
  component wb_master
17 
    port (
18 
      xtal_i      : in  std_logic;
19 
      res_i       : in  std_logic;
20 
      en_clk_o    : out std_logic;
21 
      ale_i       : in  std_logic;
22 
      rd_n_i      : in  std_logic;
23 
      wr_n_i      : in  std_logic;
24 
      sel_range_i : in  std_logic_vector( 1 downto 0);
25 
      db_bus_i    : in  std_logic_vector( 7 downto 0);
26 
      db_bus_o    : out std_logic_vector( 7 downto 0);
27 
      wb_cyc_o    : out std_logic;
28 
      wb_stb_o    : out std_logic;
29 
      wb_we_o     : out std_logic;
30 
      wb_adr_o    : out std_logic_vector(23 downto 0);
31 
      wb_ack_i    : in  std_logic;
32 
      wb_dat_i    : in  std_logic_vector( 7 downto 0);
33 
      wb_dat_o    : out std_logic_vector( 7 downto 0)
34 
    );
35 
  end component;
36 
 
37 148 arniml 
  component t8048_notri
38 153 arniml 
    generic (
39 
      gate_port_input_g : integer := 1
40 
    );
41 
 
42 148 arniml 
    port (
43 
      xtal_i       : in  std_logic;
44 
      reset_n_i    : in  std_logic;
45 
      t0_i         : in  std_logic;
46 
      t0_o         : out std_logic;
47 
      t0_dir_o     : out std_logic;
48 
      int_n_i      : in  std_logic;
49 
      ea_i         : in  std_logic;
50 
      rd_n_o       : out std_logic;
51 
      psen_n_o     : out std_logic;
52 
      wr_n_o       : out std_logic;
53 
      ale_o        : out std_logic;
54 
      db_i         : in  std_logic_vector( 7 downto 0);
55 
      db_o         : out std_logic_vector( 7 downto 0);
56 
      db_dir_o     : out std_logic;
57 
      t1_i         : in  std_logic;
58 
      p2_i         : in  std_logic_vector( 7 downto 0);
59 
      p2_o         : out std_logic_vector( 7 downto 0);
60 
      p2_low_imp_o : out std_logic;
61 
      p1_i         : in  std_logic_vector( 7 downto 0);
62 
      p1_o         : out std_logic_vector( 7 downto 0);
63 
      p1_low_imp_o : out std_logic;
64 
      prog_n_o     : out std_logic
65 
    );
66 
  end component;
67 
 
68 156 arniml 
  component t8039_notri
69 
    generic (
70 
      gate_port_input_g : integer := 1
71 
    );
72 
 
73 
    port (
74 
      xtal_i       : in  std_logic;
75 
      reset_n_i    : in  std_logic;
76 
      t0_i         : in  std_logic;
77 
      t0_o         : out std_logic;
78 
      t0_dir_o     : out std_logic;
79 
      int_n_i      : in  std_logic;
80 
      ea_i         : in  std_logic;
81 
      rd_n_o       : out std_logic;
82 
      psen_n_o     : out std_logic;
83 
      wr_n_o       : out std_logic;
84 
      ale_o        : out std_logic;
85 
      db_i         : in  std_logic_vector( 7 downto 0);
86 
      db_o         : out std_logic_vector( 7 downto 0);
87 
      db_dir_o     : out std_logic;
88 
      t1_i         : in  std_logic;
89 
      p2_i         : in  std_logic_vector( 7 downto 0);
90 
      p2_o         : out std_logic_vector( 7 downto 0);
91 
      p2_low_imp_o : out std_logic;
92 
      p1_i         : in  std_logic_vector( 7 downto 0);
93 
      p1_o         : out std_logic_vector( 7 downto 0);
94 
      p1_low_imp_o : out std_logic;
95 
      prog_n_o     : out std_logic
96 
    );
97 
  end component;
98 
 
99 165 arniml 
  component t8050_wb
100 
    generic (
101 
      gate_port_input_g : integer := 1
102 
    );
103 
 
104 
    port (
105 
      xtal_i       : in  std_logic;
106 
      reset_n_i    : in  std_logic;
107 
      t0_i         : in  std_logic;
108 
      t0_o         : out std_logic;
109 
      t0_dir_o     : out std_logic;
110 
      int_n_i      : in  std_logic;
111 
      ea_i         : in  std_logic;
112 
      rd_n_o       : out std_logic;
113 
      psen_n_o     : out std_logic;
114 
      wr_n_o       : out std_logic;
115 
      ale_o        : out std_logic;
116 
      t1_i         : in  std_logic;
117 
      p2_i         : in  std_logic_vector( 7 downto 0);
118 
      p2_o         : out std_logic_vector( 7 downto 0);
119 
      p2_low_imp_o : out std_logic;
120 
      p1_i         : in  std_logic_vector( 7 downto 0);
121 
      p1_o         : out std_logic_vector( 7 downto 0);
122 
      p1_low_imp_o : out std_logic;
123 
      prog_n_o     : out std_logic;
124 
      wb_cyc_o     : out std_logic;
125 
      wb_stb_o     : out std_logic;
126 
      wb_we_o      : out std_logic;
127 
      wb_adr_o     : out std_logic_vector(23 downto 0);
128 
      wb_ack_i     : in  std_logic;
129 
      wb_dat_i     : in  std_logic_vector( 7 downto 0);
130 
      wb_dat_o     : out std_logic_vector( 7 downto 0)
131 
    );
132 
  end component;
133 
 
134 156 arniml 
  component t8048
135 
    port (
136 
      xtal_i    : in    std_logic;
137 
      reset_n_i : in    std_logic;
138 
      t0_b      : inout std_logic;
139 
      int_n_i   : in    std_logic;
140 
      ea_i      : in    std_logic;
141 
      rd_n_o    : out   std_logic;
142 
      psen_n_o  : out   std_logic;
143 
      wr_n_o    : out   std_logic;
144 
      ale_o     : out   std_logic;
145 
      db_b      : inout std_logic_vector( 7 downto 0);
146 
      t1_i      : in    std_logic;
147 
      p2_b      : inout std_logic_vector( 7 downto 0);
148 
      p1_b      : inout std_logic_vector( 7 downto 0);
149 
      prog_n_o  : out   std_logic
150 
    );
151 
  end component;
152 
 
153 
  component t8039
154 
    port (
155 
      xtal_i    : in    std_logic;
156 
      reset_n_i : in    std_logic;
157 
      t0_b      : inout std_logic;
158 
      int_n_i   : in    std_logic;
159 
      ea_i      : in    std_logic;
160 
      rd_n_o    : out   std_logic;
161 
      psen_n_o  : out   std_logic;
162 
      wr_n_o    : out   std_logic;
163 
      ale_o     : out   std_logic;
164 
      db_b      : inout std_logic_vector( 7 downto 0);
165 
      t1_i      : in    std_logic;
166 
      p2_b      : inout std_logic_vector( 7 downto 0);
167 
      p1_b      : inout std_logic_vector( 7 downto 0);
168 
      prog_n_o  : out   std_logic
169 
    );
170 
  end component;
171 
 
172 148 arniml 
end t48_system_comp_pack;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.