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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [t48_system_comp_pack-p.vhd] - Blame information for rev 210

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-------------------------------------------------------------------------------
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--
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-- $Id: t48_system_comp_pack-p.vhd,v 1.7 2005-11-01 21:37:10 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package t48_system_comp_pack is
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  component t48_wb_master
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    port (
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      xtal_i   : in  std_logic;
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      res_i    : in  std_logic;
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      en_clk_o : out std_logic;
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      ale_i    : in  std_logic;
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      rd_n_i   : in  std_logic;
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      wr_n_i   : in  std_logic;
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      adr_i    : in  std_logic;
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      db_bus_i : in  std_logic_vector( 7 downto 0);
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      db_bus_o : out std_logic_vector( 7 downto 0);
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      wb_cyc_o : out std_logic;
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      wb_stb_o : out std_logic;
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      wb_we_o  : out std_logic;
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      wb_adr_o : out std_logic_vector(23 downto 0);
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      wb_ack_i : in  std_logic;
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      wb_dat_i : in  std_logic_vector( 7 downto 0);
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      wb_dat_o : out std_logic_vector( 7 downto 0)
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    );
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  end component;
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37 148 arniml 
  component t8048_notri
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    generic (
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      gate_port_input_g : integer := 1
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    );
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    port (
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      xtal_i        : in  std_logic;
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      reset_n_i     : in  std_logic;
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      t0_i          : in  std_logic;
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      t0_o          : out std_logic;
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      t0_dir_o      : out std_logic;
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      int_n_i       : in  std_logic;
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      ea_i          : in  std_logic;
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      rd_n_o        : out std_logic;
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      psen_n_o      : out std_logic;
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      wr_n_o        : out std_logic;
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      ale_o         : out std_logic;
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      db_i          : in  std_logic_vector( 7 downto 0);
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      db_o          : out std_logic_vector( 7 downto 0);
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      db_dir_o      : out std_logic;
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      t1_i          : in  std_logic;
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      p2_i          : in  std_logic_vector( 7 downto 0);
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      p2_o          : out std_logic_vector( 7 downto 0);
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      p2l_low_imp_o : out std_logic;
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      p2h_low_imp_o : out std_logic;
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      p1_i          : in  std_logic_vector( 7 downto 0);
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      p1_o          : out std_logic_vector( 7 downto 0);
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      p1_low_imp_o  : out std_logic;
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      prog_n_o      : out std_logic
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    );
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  end component;
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  component t8039_notri
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    generic (
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      gate_port_input_g : integer := 1
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    );
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    port (
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      xtal_i        : in  std_logic;
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      reset_n_i     : in  std_logic;
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      t0_i          : in  std_logic;
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      t0_o          : out std_logic;
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      t0_dir_o      : out std_logic;
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      int_n_i       : in  std_logic;
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      ea_i          : in  std_logic;
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      rd_n_o        : out std_logic;
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      psen_n_o      : out std_logic;
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      wr_n_o        : out std_logic;
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      ale_o         : out std_logic;
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      db_i          : in  std_logic_vector( 7 downto 0);
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      db_o          : out std_logic_vector( 7 downto 0);
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      db_dir_o      : out std_logic;
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      t1_i          : in  std_logic;
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      p2_i          : in  std_logic_vector( 7 downto 0);
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      p2_o          : out std_logic_vector( 7 downto 0);
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      p2l_low_imp_o : out std_logic;
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      p2h_low_imp_o : out std_logic;
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      p1_i          : in  std_logic_vector( 7 downto 0);
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      p1_o          : out std_logic_vector( 7 downto 0);
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      p1_low_imp_o  : out std_logic;
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      prog_n_o      : out std_logic
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    );
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  end component;
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  component t8050_wb
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    generic (
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      gate_port_input_g : integer := 1
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    );
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    port (
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      xtal_i        : in  std_logic;
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      reset_n_i     : in  std_logic;
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      t0_i          : in  std_logic;
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      t0_o          : out std_logic;
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      t0_dir_o      : out std_logic;
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      int_n_i       : in  std_logic;
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      ea_i          : in  std_logic;
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      rd_n_o        : out std_logic;
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      psen_n_o      : out std_logic;
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      wr_n_o        : out std_logic;
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      ale_o         : out std_logic;
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      t1_i          : in  std_logic;
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      p2_i          : in  std_logic_vector( 7 downto 0);
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      p2_o          : out std_logic_vector( 7 downto 0);
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      p2l_low_imp_o : out std_logic;
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      p2h_low_imp_o : out std_logic;
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      p1_i          : in  std_logic_vector( 7 downto 0);
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      p1_o          : out std_logic_vector( 7 downto 0);
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      p1_low_imp_o  : out std_logic;
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      prog_n_o      : out std_logic;
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      wb_cyc_o      : out std_logic;
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      wb_stb_o      : out std_logic;
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      wb_we_o       : out std_logic;
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      wb_adr_o      : out std_logic_vector(23 downto 0);
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      wb_ack_i      : in  std_logic;
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      wb_dat_i      : in  std_logic_vector( 7 downto 0);
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      wb_dat_o      : out std_logic_vector( 7 downto 0)
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    );
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  end component;
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  component t8048
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    port (
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      xtal_i    : in    std_logic;
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      reset_n_i : in    std_logic;
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      t0_b      : inout std_logic;
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      int_n_i   : in    std_logic;
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      ea_i      : in    std_logic;
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      rd_n_o    : out   std_logic;
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      psen_n_o  : out   std_logic;
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      wr_n_o    : out   std_logic;
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      ale_o     : out   std_logic;
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      db_b      : inout std_logic_vector( 7 downto 0);
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      t1_i      : in    std_logic;
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      p2_b      : inout std_logic_vector( 7 downto 0);
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      p1_b      : inout std_logic_vector( 7 downto 0);
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      prog_n_o  : out   std_logic
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    );
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  end component;
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  component t8039
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    port (
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      xtal_i    : in    std_logic;
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      reset_n_i : in    std_logic;
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      t0_b      : inout std_logic;
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      int_n_i   : in    std_logic;
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      ea_i      : in    std_logic;
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      rd_n_o    : out   std_logic;
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      psen_n_o  : out   std_logic;
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      wr_n_o    : out   std_logic;
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      ale_o     : out   std_logic;
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      db_b      : inout std_logic_vector( 7 downto 0);
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      t1_i      : in    std_logic;
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      p2_b      : inout std_logic_vector( 7 downto 0);
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      p1_b      : inout std_logic_vector( 7 downto 0);
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      prog_n_o  : out   std_logic
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    );
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  end component;
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end t48_system_comp_pack;

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