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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [t48_system_comp_pack-p.vhd] - Blame information for rev 292

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-------------------------------------------------------------------------------
--
-- $Id: t48_system_comp_pack-p.vhd,v 1.8 2006-06-20 00:47:08 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package t48_system_comp_pack is
 
  component t48_wb_master
    port (
      xtal_i   : in  std_logic;
      res_i    : in  std_logic;
      en_clk_o : out std_logic;
      ale_i    : in  std_logic;
      rd_n_i   : in  std_logic;
      wr_n_i   : in  std_logic;
      adr_i    : in  std_logic;
      db_bus_i : in  std_logic_vector( 7 downto 0);
      db_bus_o : out std_logic_vector( 7 downto 0);
      wb_cyc_o : out std_logic;
      wb_stb_o : out std_logic;
      wb_we_o  : out std_logic;
      wb_adr_o : out std_logic_vector(23 downto 0);
      wb_ack_i : in  std_logic;
      wb_dat_i : in  std_logic_vector( 7 downto 0);
      wb_dat_o : out std_logic_vector( 7 downto 0)
    );
  end component;
 
  component t8048_notri
    generic (
      gate_port_input_g : integer := 1
    );
 
    port (
      xtal_i        : in  std_logic;
      xtal_en_i     : in  std_logic;
      reset_n_i     : in  std_logic;
      t0_i          : in  std_logic;
      t0_o          : out std_logic;
      t0_dir_o      : out std_logic;
      int_n_i       : in  std_logic;
      ea_i          : in  std_logic;
      rd_n_o        : out std_logic;
      psen_n_o      : out std_logic;
      wr_n_o        : out std_logic;
      ale_o         : out std_logic;
      db_i          : in  std_logic_vector( 7 downto 0);
      db_o          : out std_logic_vector( 7 downto 0);
      db_dir_o      : out std_logic;
      t1_i          : in  std_logic;
      p2_i          : in  std_logic_vector( 7 downto 0);
      p2_o          : out std_logic_vector( 7 downto 0);
      p2l_low_imp_o : out std_logic;
      p2h_low_imp_o : out std_logic;
      p1_i          : in  std_logic_vector( 7 downto 0);
      p1_o          : out std_logic_vector( 7 downto 0);
      p1_low_imp_o  : out std_logic;
      prog_n_o      : out std_logic
    );
  end component;
 
  component t8039_notri
    generic (
      gate_port_input_g : integer := 1
    );
 
    port (
      xtal_i        : in  std_logic;
      xtal_en_i     : in  std_logic;
      reset_n_i     : in  std_logic;
      t0_i          : in  std_logic;
      t0_o          : out std_logic;
      t0_dir_o      : out std_logic;
      int_n_i       : in  std_logic;
      ea_i          : in  std_logic;
      rd_n_o        : out std_logic;
      psen_n_o      : out std_logic;
      wr_n_o        : out std_logic;
      ale_o         : out std_logic;
      db_i          : in  std_logic_vector( 7 downto 0);
      db_o          : out std_logic_vector( 7 downto 0);
      db_dir_o      : out std_logic;
      t1_i          : in  std_logic;
      p2_i          : in  std_logic_vector( 7 downto 0);
      p2_o          : out std_logic_vector( 7 downto 0);
      p2l_low_imp_o : out std_logic;
      p2h_low_imp_o : out std_logic;
      p1_i          : in  std_logic_vector( 7 downto 0);
      p1_o          : out std_logic_vector( 7 downto 0);
      p1_low_imp_o  : out std_logic;
      prog_n_o      : out std_logic
    );
  end component;
 
  component t8050_wb
    generic (
      gate_port_input_g : integer := 1
    );
 
    port (
      xtal_i        : in  std_logic;
      reset_n_i     : in  std_logic;
      t0_i          : in  std_logic;
      t0_o          : out std_logic;
      t0_dir_o      : out std_logic;
      int_n_i       : in  std_logic;
      ea_i          : in  std_logic;
      rd_n_o        : out std_logic;
      psen_n_o      : out std_logic;
      wr_n_o        : out std_logic;
      ale_o         : out std_logic;
      t1_i          : in  std_logic;
      p2_i          : in  std_logic_vector( 7 downto 0);
      p2_o          : out std_logic_vector( 7 downto 0);
      p2l_low_imp_o : out std_logic;
      p2h_low_imp_o : out std_logic;
      p1_i          : in  std_logic_vector( 7 downto 0);
      p1_o          : out std_logic_vector( 7 downto 0);
      p1_low_imp_o  : out std_logic;
      prog_n_o      : out std_logic;
      wb_cyc_o      : out std_logic;
      wb_stb_o      : out std_logic;
      wb_we_o       : out std_logic;
      wb_adr_o      : out std_logic_vector(23 downto 0);
      wb_ack_i      : in  std_logic;
      wb_dat_i      : in  std_logic_vector( 7 downto 0);
      wb_dat_o      : out std_logic_vector( 7 downto 0)
    );
  end component;
 
  component t8048
    port (
      xtal_i    : in    std_logic;
      reset_n_i : in    std_logic;
      t0_b      : inout std_logic;
      int_n_i   : in    std_logic;
      ea_i      : in    std_logic;
      rd_n_o    : out   std_logic;
      psen_n_o  : out   std_logic;
      wr_n_o    : out   std_logic;
      ale_o     : out   std_logic;
      db_b      : inout std_logic_vector( 7 downto 0);
      t1_i      : in    std_logic;
      p2_b      : inout std_logic_vector( 7 downto 0);
      p1_b      : inout std_logic_vector( 7 downto 0);
      prog_n_o  : out   std_logic
    );
  end component;
 
  component t8039
    port (
      xtal_i    : in    std_logic;
      reset_n_i : in    std_logic;
      t0_b      : inout std_logic;
      int_n_i   : in    std_logic;
      ea_i      : in    std_logic;
      rd_n_o    : out   std_logic;
      psen_n_o  : out   std_logic;
      wr_n_o    : out   std_logic;
      ale_o     : out   std_logic;
      db_b      : inout std_logic_vector( 7 downto 0);
      t1_i      : in    std_logic;
      p2_b      : inout std_logic_vector( 7 downto 0);
      p1_b      : inout std_logic_vector( 7 downto 0);
      prog_n_o  : out   std_logic
    );
  end component;
 
end t48_system_comp_pack;

Line No.	Rev	Author	Line
1	148	arniml	`-------------------------------------------------------------------------------`
2			`--`
3	220	arniml	`-- $Id: t48_system_comp_pack-p.vhd,v 1.8 2006-06-20 00:47:08 arniml Exp $`
4	148	arniml	`--`
5			`-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)`
6			`--`
7			`-- All rights reserved`
8			`--`
9			`-------------------------------------------------------------------------------`
10
11			`library ieee;`
12			`use ieee.std_logic_1164.all;`
13
14			`package t48_system_comp_pack is`
15
16	180	arniml	`component t48_wb_master`
17	165	arniml	`port (`
18	168	arniml	`xtal_i : in std_logic;`
19			`res_i : in std_logic;`
20			`en_clk_o : out std_logic;`
21			`ale_i : in std_logic;`
22			`rd_n_i : in std_logic;`
23			`wr_n_i : in std_logic;`
24			`adr_i : in std_logic;`
25			`db_bus_i : in std_logic_vector( 7 downto 0);`
26			`db_bus_o : out std_logic_vector( 7 downto 0);`
27			`wb_cyc_o : out std_logic;`
28			`wb_stb_o : out std_logic;`
29			`wb_we_o : out std_logic;`
30			`wb_adr_o : out std_logic_vector(23 downto 0);`
31			`wb_ack_i : in std_logic;`
32			`wb_dat_i : in std_logic_vector( 7 downto 0);`
33			`wb_dat_o : out std_logic_vector( 7 downto 0)`
34	165	arniml	`);`
35			`end component;`
36
37	148	arniml	`component t8048_notri`
38	153	arniml	`generic (`
39			`gate_port_input_g : integer := 1`
40			`);`
41
42	148	arniml	`port (`
43	210	arniml	`xtal_i : in std_logic;`
44	220	arniml	`xtal_en_i : in std_logic;`
45	210	arniml	`reset_n_i : in std_logic;`
46			`t0_i : in std_logic;`
47			`t0_o : out std_logic;`
48			`t0_dir_o : out std_logic;`
49			`int_n_i : in std_logic;`
50			`ea_i : in std_logic;`
51			`rd_n_o : out std_logic;`
52			`psen_n_o : out std_logic;`
53			`wr_n_o : out std_logic;`
54			`ale_o : out std_logic;`
55			`db_i : in std_logic_vector( 7 downto 0);`
56			`db_o : out std_logic_vector( 7 downto 0);`
57			`db_dir_o : out std_logic;`
58			`t1_i : in std_logic;`
59			`p2_i : in std_logic_vector( 7 downto 0);`
60			`p2_o : out std_logic_vector( 7 downto 0);`
61			`p2l_low_imp_o : out std_logic;`
62			`p2h_low_imp_o : out std_logic;`
63			`p1_i : in std_logic_vector( 7 downto 0);`
64			`p1_o : out std_logic_vector( 7 downto 0);`
65			`p1_low_imp_o : out std_logic;`
66			`prog_n_o : out std_logic`
67	148	arniml	`);`
68			`end component;`
69
70	156	arniml	`component t8039_notri`
71			`generic (`
72			`gate_port_input_g : integer := 1`
73			`);`
74
75			`port (`
76	210	arniml	`xtal_i : in std_logic;`
77	220	arniml	`xtal_en_i : in std_logic;`
78	210	arniml	`reset_n_i : in std_logic;`
79			`t0_i : in std_logic;`
80			`t0_o : out std_logic;`
81			`t0_dir_o : out std_logic;`
82			`int_n_i : in std_logic;`
83			`ea_i : in std_logic;`
84			`rd_n_o : out std_logic;`
85			`psen_n_o : out std_logic;`
86			`wr_n_o : out std_logic;`
87			`ale_o : out std_logic;`
88			`db_i : in std_logic_vector( 7 downto 0);`
89			`db_o : out std_logic_vector( 7 downto 0);`
90			`db_dir_o : out std_logic;`
91			`t1_i : in std_logic;`
92			`p2_i : in std_logic_vector( 7 downto 0);`
93			`p2_o : out std_logic_vector( 7 downto 0);`
94			`p2l_low_imp_o : out std_logic;`
95			`p2h_low_imp_o : out std_logic;`
96			`p1_i : in std_logic_vector( 7 downto 0);`
97			`p1_o : out std_logic_vector( 7 downto 0);`
98			`p1_low_imp_o : out std_logic;`
99			`prog_n_o : out std_logic`
100	156	arniml	`);`
101			`end component;`
102
103	165	arniml	`component t8050_wb`
104			`generic (`
105			`gate_port_input_g : integer := 1`
106			`);`
107
108			`port (`
109	210	arniml	`xtal_i : in std_logic;`
110			`reset_n_i : in std_logic;`
111			`t0_i : in std_logic;`
112			`t0_o : out std_logic;`
113			`t0_dir_o : out std_logic;`
114			`int_n_i : in std_logic;`
115			`ea_i : in std_logic;`
116			`rd_n_o : out std_logic;`
117			`psen_n_o : out std_logic;`
118			`wr_n_o : out std_logic;`
119			`ale_o : out std_logic;`
120			`t1_i : in std_logic;`
121			`p2_i : in std_logic_vector( 7 downto 0);`
122			`p2_o : out std_logic_vector( 7 downto 0);`
123			`p2l_low_imp_o : out std_logic;`
124			`p2h_low_imp_o : out std_logic;`
125			`p1_i : in std_logic_vector( 7 downto 0);`
126			`p1_o : out std_logic_vector( 7 downto 0);`
127			`p1_low_imp_o : out std_logic;`
128			`prog_n_o : out std_logic;`
129			`wb_cyc_o : out std_logic;`
130			`wb_stb_o : out std_logic;`
131			`wb_we_o : out std_logic;`
132			`wb_adr_o : out std_logic_vector(23 downto 0);`
133			`wb_ack_i : in std_logic;`
134			`wb_dat_i : in std_logic_vector( 7 downto 0);`
135			`wb_dat_o : out std_logic_vector( 7 downto 0)`
136	165	arniml	`);`
137			`end component;`
138
139	156	arniml	`component t8048`
140			`port (`
141			`xtal_i : in std_logic;`
142			`reset_n_i : in std_logic;`
143			`t0_b : inout std_logic;`
144			`int_n_i : in std_logic;`
145			`ea_i : in std_logic;`
146			`rd_n_o : out std_logic;`
147			`psen_n_o : out std_logic;`
148			`wr_n_o : out std_logic;`
149			`ale_o : out std_logic;`
150			`db_b : inout std_logic_vector( 7 downto 0);`
151			`t1_i : in std_logic;`
152			`p2_b : inout std_logic_vector( 7 downto 0);`
153			`p1_b : inout std_logic_vector( 7 downto 0);`
154			`prog_n_o : out std_logic`
155			`);`
156			`end component;`
157
158			`component t8039`
159			`port (`
160			`xtal_i : in std_logic;`
161			`reset_n_i : in std_logic;`
162			`t0_b : inout std_logic;`
163			`int_n_i : in std_logic;`
164			`ea_i : in std_logic;`
165			`rd_n_o : out std_logic;`
166			`psen_n_o : out std_logic;`
167			`wr_n_o : out std_logic;`
168			`ale_o : out std_logic;`
169			`db_b : inout std_logic_vector( 7 downto 0);`
170			`t1_i : in std_logic;`
171			`p2_b : inout std_logic_vector( 7 downto 0);`
172			`p1_b : inout std_logic_vector( 7 downto 0);`
173			`prog_n_o : out std_logic`
174			`);`
175			`end component;`
176
177	148	arniml	`end t48_system_comp_pack;`

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [t48_system_comp_pack-p.vhd] - Blame information for rev 292