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-------------------------------------------------------------------------------
--
-- $Id: t48_comp_pack-p.vhd,v 1.11 2006-06-20 00:46:04 arniml Exp $
--
-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.t48_alu_pack.alu_op_t;
use work.t48_cond_branch_pack.branch_conditions_t;
use work.t48_cond_branch_pack.comp_value_t;
use work.t48_decoder_pack.mnemonic_t;
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;
use work.t48_pack.dmem_addr_t;
use work.t48_pack.pmem_addr_t;
use work.t48_pack.mstate_t;
use work.t48_pack.word_t;
use work.t48_pack.nibble_t;
 
package t48_comp_pack is
 
  component t48_alu
    port (
      clk_i              : in  std_logic;
      res_i              : in  std_logic;
      en_clk_i           : in  boolean;
      data_i             : in  word_t;
      data_o             : out word_t;
      write_accu_i       : in  boolean;
      write_shadow_i     : in  boolean;
      write_temp_reg_i   : in  boolean;
      read_alu_i         : in  boolean;
      carry_i            : in  std_logic;
      carry_o            : out std_logic;
      aux_carry_o        : out std_logic;
      alu_op_i           : in  alu_op_t;
      use_carry_i        : in  boolean;
      da_high_i          : in  boolean;
      da_overflow_o      : out boolean;
      accu_low_i         : in  boolean;
      p06_temp_reg_i     : in  boolean;
      p60_temp_reg_i     : in  boolean
    );
  end component;
 
  component t48_bus_mux
    port (
      alu_data_i : in  word_t;
      bus_data_i : in  word_t;
      dec_data_i : in  word_t;
      dm_data_i  : in  word_t;
      pm_data_i  : in  word_t;
      p1_data_i  : in  word_t;
      p2_data_i  : in  word_t;
      psw_data_i : in  word_t;
      tim_data_i : in  word_t;
      data_o     : out word_t
    );
  end component;
 
  component t48_clock_ctrl
    generic (
      xtal_div_3_g   : integer := 1
    );
    port (
      clk_i          : in  std_logic;
      xtal_i         : in  std_logic;
      xtal_en_i      : in  boolean;
      res_i          : in  std_logic;
      en_clk_i       : in  boolean;
      xtal3_o        : out boolean;
      t0_o           : out std_logic;
      multi_cycle_i  : in  boolean;
      assert_psen_i  : in  boolean;
      assert_prog_i  : in  boolean;
      assert_rd_i    : in  boolean;
      assert_wr_i    : in  boolean;
      mstate_o       : out mstate_t;
      second_cycle_o : out boolean;
      ale_o          : out boolean;
      psen_o         : out boolean;
      prog_o         : out boolean;
      rd_o           : out boolean;
      wr_o           : out boolean
    );
  end component;
 
  component t48_cond_branch
    port (
      clk_i          : in  std_logic;
      res_i          : in  std_logic;
      en_clk_i       : in  boolean;
      compute_take_i : in  boolean;
      branch_cond_i  : in  branch_conditions_t;
      take_branch_o  : out boolean;
      accu_i         : in  word_t;
      t0_i           : in  std_logic;
      t1_i           : in  std_logic;
      int_n_i        : in  std_logic;
      f0_i           : in  std_logic;
      f1_i           : in  std_logic;
      tf_i           : in  std_logic;
      carry_i        : in  std_logic;
      comp_value_i   : in  comp_value_t
    );
  end component;
 
  component t48_db_bus
    port (
      clk_i        : in  std_logic;
      res_i        : in  std_logic;
      en_clk_i     : in  boolean;
      ea_i         : in  std_logic;
      data_i       : in  word_t;
      data_o       : out word_t;
      write_bus_i  : in  boolean;
      read_bus_i   : in  boolean;
      output_pcl_i : in  boolean;
      bidir_bus_i  : in  boolean;
      pcl_i        : in  word_t;
      db_i         : in  word_t;
      db_o         : out word_t;
      db_dir_o     : out std_logic
    );
  end component;
 
  component t48_decoder
    generic (
      register_mnemonic_g   : integer := 1
    );
    port (
      clk_i                  : in  std_logic;
      res_i                  : in  std_logic;
      en_clk_i               : in  boolean;
      xtal_i                 : in  std_logic;
      xtal_en_i              : in  boolean;
      ea_i                   : in  std_logic;
      ale_i                  : in  boolean;
      int_n_i                : in  std_logic;
      t0_dir_o               : out std_logic;
      data_i                 : in  word_t;
      data_o                 : out word_t;
      alu_write_accu_o       : out boolean;
      alu_write_shadow_o     : out boolean;
      alu_write_temp_reg_o   : out boolean;
      alu_read_alu_o         : out boolean;
      bus_write_bus_o        : out boolean;
      bus_read_bus_o         : out boolean;
      dm_write_dmem_addr_o   : out boolean;
      dm_write_dmem_o        : out boolean;
      dm_read_dmem_o         : out boolean;
      p1_write_p1_o          : out boolean;
      p1_read_p1_o           : out boolean;
      p2_write_p2_o          : out boolean;
      p2_write_exp_o         : out boolean;
      p2_read_p2_o           : out boolean;
      pm_write_pcl_o         : out boolean;
      pm_read_pcl_o          : out boolean;
      pm_write_pch_o         : out boolean;
      pm_read_pch_o          : out boolean;
      pm_read_pmem_o         : out boolean;
      psw_read_psw_o         : out boolean;
      psw_read_sp_o          : out boolean;
      psw_write_psw_o        : out boolean;
      psw_write_sp_o         : out boolean;
      alu_carry_i            : in  std_logic;
      alu_op_o               : out alu_op_t;
      alu_da_high_o          : out boolean;
      alu_accu_low_o         : out boolean;
      alu_da_overflow_i      : in  boolean;
      alu_p06_temp_reg_o     : out boolean;
      alu_p60_temp_reg_o     : out boolean;
      alu_use_carry_o        : out boolean;
      bus_output_pcl_o       : out boolean;
      bus_bidir_bus_o        : out boolean;
      clk_multi_cycle_o      : out boolean;
      clk_assert_psen_o      : out boolean;
      clk_assert_prog_o      : out boolean;
      clk_assert_rd_o        : out boolean;
      clk_assert_wr_o        : out boolean;
      clk_mstate_i           : in  mstate_t;
      clk_second_cycle_i     : in  boolean;
      cnd_compute_take_o     : out boolean;
      cnd_branch_cond_o      : out branch_conditions_t;
      cnd_take_branch_i      : in  boolean;
      cnd_comp_value_o       : out comp_value_t;
      cnd_f1_o               : out std_logic;
      cnd_tf_o               : out std_logic;
      dm_addr_type_o         : out dmem_addr_ident_t;
      tim_read_timer_o       : out boolean;
      tim_write_timer_o      : out boolean;
      tim_start_t_o          : out boolean;
      tim_start_cnt_o        : out boolean;
      tim_stop_tcnt_o        : out boolean;
      p1_read_reg_o          : out boolean;
      p2_read_reg_o          : out boolean;
      p2_read_exp_o          : out boolean;
      p2_output_pch_o        : out boolean;
      pm_inc_pc_o            : out boolean;
      pm_write_pmem_addr_o   : out boolean;
      pm_addr_type_o         : out pmem_addr_ident_t;
      psw_special_data_o     : out std_logic;
      psw_carry_i            : in  std_logic;
      psw_aux_carry_i        : in  std_logic;
      psw_f0_i               : in  std_logic;
      psw_inc_stackp_o       : out boolean;
      psw_dec_stackp_o       : out boolean;
      psw_write_carry_o      : out boolean;
      psw_write_aux_carry_o  : out boolean;
      psw_write_f0_o         : out boolean;
      psw_write_bs_o         : out boolean;
      tim_overflow_i         : in  boolean
    );
  end component;
 
  component t48_dmem_ctrl
    port (
      clk_i             : in  std_logic;
      res_i             : in  std_logic;
      en_clk_i          : in  boolean;
      data_i            : in  word_t;
      write_dmem_addr_i : in  boolean;
      write_dmem_i      : in  boolean;
      read_dmem_i       : in  boolean;
      addr_type_i       : in  dmem_addr_ident_t;
      bank_select_i     : in  std_logic;
      data_o            : out word_t;
      dmem_data_i       : in  word_t;
      dmem_addr_o       : out dmem_addr_t;
      dmem_we_o         : out std_logic;
      dmem_data_o       : out word_t
    );
  end component;
 
  component t48_int
    port (
      clk_i             : in  std_logic;
      res_i             : in  std_logic;
      en_clk_i          : in  boolean;
      xtal_i            : in  std_logic;
      xtal_en_i         : in  boolean;
      clk_mstate_i      : in  mstate_t;
      jtf_executed_i    : in  boolean;
      tim_overflow_i    : in  boolean;
      tf_o              : out std_logic;
      en_tcnti_i        : in  boolean;
      dis_tcnti_i       : in  boolean;
      int_n_i           : in  std_logic;
      ale_i             : in  boolean;
      last_cycle_i      : in  boolean;
      en_i_i            : in  boolean;
      dis_i_i           : in  boolean;
      ext_int_o         : out boolean;
      tim_int_o         : out boolean;
      retr_executed_i   : in  boolean;
      int_executed_i    : in  boolean;
      int_pending_o     : out boolean;
      int_in_progress_o : out boolean
    );
  end component;
 
  component t48_opc_table
    port (
      opcode_i      : in  word_t;
      multi_cycle_o : out std_logic;
      mnemonic_o    : out mnemonic_t
    );
  end component;
 
  component t48_opc_decoder
    generic (
      register_mnemonic_g : integer := 1
    );
    port (
      clk_i         : in  std_logic;
      res_i         : in  std_logic;
      en_clk_i      : in  boolean;
      data_i        : in  word_t;
      read_bus_i    : in  boolean;
      inj_int_i     : in  boolean;
      opcode_o      : out word_t;
      mnemonic_o    : out mnemonic_t;
      multi_cycle_o : out boolean
    );
  end component;
 
  component t48_timer
    generic (
      sample_t1_state_g : integer := 4
    );
    port (
      clk_i         : in  std_logic;
      res_i         : in  std_logic;
      en_clk_i      : in  boolean;
      t1_i          : in  std_logic;
      clk_mstate_i  : in  mstate_t;
      data_i        : in  word_t;
      data_o        : out word_t;
      read_timer_i  : in  boolean;
      write_timer_i : in  boolean;
      start_t_i     : in  boolean;
      start_cnt_i   : in  boolean;
      stop_tcnt_i   : in  boolean;
      overflow_o    : out std_logic
    );
  end component;
 
  component t48_p1
    port (
      clk_i        : in  std_logic;
      res_i        : in  std_logic;
      en_clk_i     : in  boolean;
      data_i       : in  word_t;
      data_o       : out word_t;
      write_p1_i   : in  boolean;
      read_p1_i    : in  boolean;
      read_reg_i   : in  boolean;
      p1_i         : in  word_t;
      p1_o         : out word_t;
      p1_low_imp_o : out std_logic
    );
  end component;
 
  component t48_p2
    port (
      clk_i         : in  std_logic;
      res_i         : in  std_logic;
      en_clk_i      : in  boolean;
      xtal_i        : in  std_logic;
      xtal_en_i     : in  boolean;
      data_i        : in  word_t;
      data_o        : out word_t;
      write_p2_i    : in  boolean;
      write_exp_i   : in  boolean;
      read_p2_i     : in  boolean;
      read_reg_i    : in  boolean;
      read_exp_i    : in  boolean;
      output_pch_i  : in  boolean;
      pch_i         : in  nibble_t;
      p2_i          : in  word_t;
      p2_o          : out word_t;
      p2l_low_imp_o : out std_logic;
      p2h_low_imp_o : out std_logic
    );
  end component;
 
  component t48_pmem_ctrl
    port (
      clk_i             : in  std_logic;
      res_i             : in  std_logic;
      en_clk_i          : in  boolean;
      data_i            : in  word_t;
      data_o            : out word_t;
      write_pcl_i       : in  boolean;
      read_pcl_i        : in  boolean;
      write_pch_i       : in  boolean;
      read_pch_i        : in  boolean;
      inc_pc_i          : in  boolean;
      write_pmem_addr_i : in  boolean;
      addr_type_i       : in  pmem_addr_ident_t;
      read_pmem_i       : in  boolean;
      pmem_addr_o       : out pmem_addr_t;
      pmem_data_i       : in  word_t
    );
  end component;
 
  component t48_psw
    port (
      clk_i              : in  std_logic;
      res_i              : in  std_logic;
      en_clk_i           : in  boolean;
      data_i             : in  word_t;
      data_o             : out word_t;
      read_psw_i         : in  boolean;
      read_sp_i          : in  boolean;
      write_psw_i        : in  boolean;
      write_sp_i         : in  boolean;
      special_data_i     : in  std_logic;
      inc_stackp_i       : in  boolean;
      dec_stackp_i       : in  boolean;
      write_carry_i      : in  boolean;
      write_aux_carry_i  : in  boolean;
      write_f0_i         : in  boolean;
      write_bs_i         : in  boolean;
      carry_o            : out std_logic;
      aux_carry_i        : in  std_logic;
      aux_carry_o        : out std_logic;
      f0_o               : out std_logic;
      bs_o               : out std_logic
    );
  end component;
 
end t48_comp_pack;

Line No.	Rev	Author	Line
1	4	arniml	`-------------------------------------------------------------------------------`
2			`--`
3	220	arniml	`-- $Id: t48_comp_pack-p.vhd,v 1.11 2006-06-20 00:46:04 arniml Exp $`
4	4	arniml	`--`
5	162	arniml	`-- Copyright (c) 2004, 2005, Arnim Laeuger (arniml@opencores.org)`
6	4	arniml	`--`
7			`-- All rights reserved`
8			`--`
9			`-------------------------------------------------------------------------------`
10
11			`library ieee;`
12			`use ieee.std_logic_1164.all;`
13
14	179	arniml	`use work.t48_alu_pack.alu_op_t;`
15			`use work.t48_cond_branch_pack.branch_conditions_t;`
16			`use work.t48_cond_branch_pack.comp_value_t;`
17			`use work.t48_decoder_pack.mnemonic_t;`
18			`use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;`
19			`use work.t48_pmem_ctrl_pack.pmem_addr_ident_t;`
20	4	arniml	`use work.t48_pack.dmem_addr_t;`
21			`use work.t48_pack.pmem_addr_t;`
22			`use work.t48_pack.mstate_t;`
23			`use work.t48_pack.word_t;`
24			`use work.t48_pack.nibble_t;`
25
26			`package t48_comp_pack is`
27
28	179	arniml	`component t48_alu`
29	4	arniml	`port (`
30			`clk_i : in std_logic;`
31			`res_i : in std_logic;`
32			`en_clk_i : in boolean;`
33			`data_i : in word_t;`
34			`data_o : out word_t;`
35			`write_accu_i : in boolean;`
36			`write_shadow_i : in boolean;`
37			`write_temp_reg_i : in boolean;`
38			`read_alu_i : in boolean;`
39			`carry_i : in std_logic;`
40			`carry_o : out std_logic;`
41			`aux_carry_o : out std_logic;`
42			`alu_op_i : in alu_op_t;`
43	28	arniml	`use_carry_i : in boolean;`
44			`da_high_i : in boolean;`
45			`da_overflow_o : out boolean;`
46	38	arniml	`accu_low_i : in boolean;`
47	28	arniml	`p06_temp_reg_i : in boolean;`
48			`p60_temp_reg_i : in boolean`
49	4	arniml	`);`
50			`end component;`
51
52	179	arniml	`component t48_bus_mux`
53	4	arniml	`port (`
54			`alu_data_i : in word_t;`
55			`bus_data_i : in word_t;`
56			`dec_data_i : in word_t;`
57			`dm_data_i : in word_t;`
58			`pm_data_i : in word_t;`
59			`p1_data_i : in word_t;`
60			`p2_data_i : in word_t;`
61			`psw_data_i : in word_t;`
62			`tim_data_i : in word_t;`
63			`data_o : out word_t`
64			`);`
65			`end component;`
66
67	179	arniml	`component t48_clock_ctrl`
68	4	arniml	`generic (`
69			`xtal_div_3_g : integer := 1`
70			`);`
71			`port (`
72			`clk_i : in std_logic;`
73			`xtal_i : in std_logic;`
74	220	arniml	`xtal_en_i : in boolean;`
75	4	arniml	`res_i : in std_logic;`
76			`en_clk_i : in boolean;`
77			`xtal3_o : out boolean;`
78	162	arniml	`t0_o : out std_logic;`
79	4	arniml	`multi_cycle_i : in boolean;`
80			`assert_psen_i : in boolean;`
81			`assert_prog_i : in boolean;`
82			`assert_rd_i : in boolean;`
83			`assert_wr_i : in boolean;`
84			`mstate_o : out mstate_t;`
85			`second_cycle_o : out boolean;`
86			`ale_o : out boolean;`
87			`psen_o : out boolean;`
88			`prog_o : out boolean;`
89			`rd_o : out boolean;`
90			`wr_o : out boolean`
91			`);`
92			`end component;`
93
94	179	arniml	`component t48_cond_branch`
95	4	arniml	`port (`
96			`clk_i : in std_logic;`
97			`res_i : in std_logic;`
98			`en_clk_i : in boolean;`
99			`compute_take_i : in boolean;`
100			`branch_cond_i : in branch_conditions_t;`
101			`take_branch_o : out boolean;`
102			`accu_i : in word_t;`
103			`t0_i : in std_logic;`
104			`t1_i : in std_logic;`
105			`int_n_i : in std_logic;`
106			`f0_i : in std_logic;`
107			`f1_i : in std_logic;`
108			`tf_i : in std_logic;`
109			`carry_i : in std_logic;`
110			`comp_value_i : in comp_value_t`
111			`);`
112			`end component;`
113
114	179	arniml	`component t48_db_bus`
115	4	arniml	`port (`
116			`clk_i : in std_logic;`
117			`res_i : in std_logic;`
118			`en_clk_i : in boolean;`
119			`ea_i : in std_logic;`
120			`data_i : in word_t;`
121			`data_o : out word_t;`
122			`write_bus_i : in boolean;`
123			`read_bus_i : in boolean;`
124			`output_pcl_i : in boolean;`
125			`bidir_bus_i : in boolean;`
126			`pcl_i : in word_t;`
127			`db_i : in word_t;`
128			`db_o : out word_t;`
129			`db_dir_o : out std_logic`
130			`);`
131			`end component;`
132
133	179	arniml	`component t48_decoder`
134	4	arniml	`generic (`
135			`register_mnemonic_g : integer := 1`
136			`);`
137			`port (`
138			`clk_i : in std_logic;`
139			`res_i : in std_logic;`
140			`en_clk_i : in boolean;`
141	207	arniml	`xtal_i : in std_logic;`
142	220	arniml	`xtal_en_i : in boolean;`
143	4	arniml	`ea_i : in std_logic;`
144			`ale_i : in boolean;`
145			`int_n_i : in std_logic;`
146			`t0_dir_o : out std_logic;`
147			`data_i : in word_t;`
148			`data_o : out word_t;`
149			`alu_write_accu_o : out boolean;`
150			`alu_write_shadow_o : out boolean;`
151			`alu_write_temp_reg_o : out boolean;`
152			`alu_read_alu_o : out boolean;`
153			`bus_write_bus_o : out boolean;`
154			`bus_read_bus_o : out boolean;`
155			`dm_write_dmem_addr_o : out boolean;`
156			`dm_write_dmem_o : out boolean;`
157			`dm_read_dmem_o : out boolean;`
158			`p1_write_p1_o : out boolean;`
159			`p1_read_p1_o : out boolean;`
160			`p2_write_p2_o : out boolean;`
161			`p2_write_exp_o : out boolean;`
162			`p2_read_p2_o : out boolean;`
163			`pm_write_pcl_o : out boolean;`
164			`pm_read_pcl_o : out boolean;`
165			`pm_write_pch_o : out boolean;`
166			`pm_read_pch_o : out boolean;`
167			`pm_read_pmem_o : out boolean;`
168			`psw_read_psw_o : out boolean;`
169			`psw_read_sp_o : out boolean;`
170			`psw_write_psw_o : out boolean;`
171			`psw_write_sp_o : out boolean;`
172			`alu_carry_i : in std_logic;`
173			`alu_op_o : out alu_op_t;`
174	28	arniml	`alu_da_high_o : out boolean;`
175	38	arniml	`alu_accu_low_o : out boolean;`
176	28	arniml	`alu_da_overflow_i : in boolean;`
177			`alu_p06_temp_reg_o : out boolean;`
178			`alu_p60_temp_reg_o : out boolean;`
179	4	arniml	`alu_use_carry_o : out boolean;`
180			`bus_output_pcl_o : out boolean;`
181			`bus_bidir_bus_o : out boolean;`
182			`clk_multi_cycle_o : out boolean;`
183			`clk_assert_psen_o : out boolean;`
184			`clk_assert_prog_o : out boolean;`
185			`clk_assert_rd_o : out boolean;`
186			`clk_assert_wr_o : out boolean;`
187			`clk_mstate_i : in mstate_t;`
188			`clk_second_cycle_i : in boolean;`
189			`cnd_compute_take_o : out boolean;`
190			`cnd_branch_cond_o : out branch_conditions_t;`
191			`cnd_take_branch_i : in boolean;`
192			`cnd_comp_value_o : out comp_value_t;`
193			`cnd_f1_o : out std_logic;`
194			`cnd_tf_o : out std_logic;`
195			`dm_addr_type_o : out dmem_addr_ident_t;`
196			`tim_read_timer_o : out boolean;`
197			`tim_write_timer_o : out boolean;`
198			`tim_start_t_o : out boolean;`
199			`tim_start_cnt_o : out boolean;`
200			`tim_stop_tcnt_o : out boolean;`
201			`p1_read_reg_o : out boolean;`
202			`p2_read_reg_o : out boolean;`
203	24	arniml	`p2_read_exp_o : out boolean;`
204	4	arniml	`p2_output_pch_o : out boolean;`
205			`pm_inc_pc_o : out boolean;`
206			`pm_write_pmem_addr_o : out boolean;`
207			`pm_addr_type_o : out pmem_addr_ident_t;`
208			`psw_special_data_o : out std_logic;`
209			`psw_carry_i : in std_logic;`
210	28	arniml	`psw_aux_carry_i : in std_logic;`
211	4	arniml	`psw_f0_i : in std_logic;`
212			`psw_inc_stackp_o : out boolean;`
213			`psw_dec_stackp_o : out boolean;`
214			`psw_write_carry_o : out boolean;`
215			`psw_write_aux_carry_o : out boolean;`
216			`psw_write_f0_o : out boolean;`
217			`psw_write_bs_o : out boolean;`
218			`tim_overflow_i : in boolean`
219			`);`
220			`end component;`
221
222	179	arniml	`component t48_dmem_ctrl`
223	4	arniml	`port (`
224			`clk_i : in std_logic;`
225			`res_i : in std_logic;`
226			`en_clk_i : in boolean;`
227			`data_i : in word_t;`
228			`write_dmem_addr_i : in boolean;`
229			`write_dmem_i : in boolean;`
230			`read_dmem_i : in boolean;`
231			`addr_type_i : in dmem_addr_ident_t;`
232			`bank_select_i : in std_logic;`
233			`data_o : out word_t;`
234			`dmem_data_i : in word_t;`
235			`dmem_addr_o : out dmem_addr_t;`
236			`dmem_we_o : out std_logic;`
237			`dmem_data_o : out word_t`
238			`);`
239			`end component;`
240
241	179	arniml	`component t48_int`
242	4	arniml	`port (`
243	119	arniml	`clk_i : in std_logic;`
244			`res_i : in std_logic;`
245			`en_clk_i : in boolean;`
246	207	arniml	`xtal_i : in std_logic;`
247	220	arniml	`xtal_en_i : in boolean;`
248	119	arniml	`clk_mstate_i : in mstate_t;`
249			`jtf_executed_i : in boolean;`
250			`tim_overflow_i : in boolean;`
251			`tf_o : out std_logic;`
252			`en_tcnti_i : in boolean;`
253			`dis_tcnti_i : in boolean;`
254			`int_n_i : in std_logic;`
255			`ale_i : in boolean;`
256			`last_cycle_i : in boolean;`
257			`en_i_i : in boolean;`
258			`dis_i_i : in boolean;`
259			`ext_int_o : out boolean;`
260			`tim_int_o : out boolean;`
261			`retr_executed_i : in boolean;`
262			`int_executed_i : in boolean;`
263			`int_pending_o : out boolean;`
264			`int_in_progress_o : out boolean`
265	4	arniml	`);`
266			`end component;`
267
268	179	arniml	`component t48_opc_table`
269	4	arniml	`port (`
270			`opcode_i : in word_t;`
271			`multi_cycle_o : out std_logic;`
272			`mnemonic_o : out mnemonic_t`
273			`);`
274			`end component;`
275
276	179	arniml	`component t48_opc_decoder`
277	4	arniml	`generic (`
278			`register_mnemonic_g : integer := 1`
279			`);`
280			`port (`
281			`clk_i : in std_logic;`
282			`res_i : in std_logic;`
283			`en_clk_i : in boolean;`
284			`data_i : in word_t;`
285			`read_bus_i : in boolean;`
286			`inj_int_i : in boolean;`
287			`opcode_o : out word_t;`
288			`mnemonic_o : out mnemonic_t;`
289			`multi_cycle_o : out boolean`
290			`);`
291			`end component;`
292
293	179	arniml	`component t48_timer`
294	4	arniml	`generic (`
295			`sample_t1_state_g : integer := 4`
296			`);`
297			`port (`
298			`clk_i : in std_logic;`
299			`res_i : in std_logic;`
300			`en_clk_i : in boolean;`
301			`t1_i : in std_logic;`
302			`clk_mstate_i : in mstate_t;`
303			`data_i : in word_t;`
304			`data_o : out word_t;`
305			`read_timer_i : in boolean;`
306			`write_timer_i : in boolean;`
307			`start_t_i : in boolean;`
308			`start_cnt_i : in boolean;`
309			`stop_tcnt_i : in boolean;`
310			`overflow_o : out std_logic`
311			`);`
312			`end component;`
313
314	179	arniml	`component t48_p1`
315	4	arniml	`port (`
316	32	arniml	`clk_i : in std_logic;`
317			`res_i : in std_logic;`
318			`en_clk_i : in boolean;`
319			`data_i : in word_t;`
320			`data_o : out word_t;`
321			`write_p1_i : in boolean;`
322			`read_p1_i : in boolean;`
323			`read_reg_i : in boolean;`
324			`p1_i : in word_t;`
325			`p1_o : out word_t;`
326			`p1_low_imp_o : out std_logic`
327	4	arniml	`);`
328			`end component;`
329
330	179	arniml	`component t48_p2`
331	4	arniml	`port (`
332	207	arniml	`clk_i : in std_logic;`
333			`res_i : in std_logic;`
334			`en_clk_i : in boolean;`
335			`xtal_i : in std_logic;`
336	220	arniml	`xtal_en_i : in boolean;`
337	207	arniml	`data_i : in word_t;`
338			`data_o : out word_t;`
339			`write_p2_i : in boolean;`
340			`write_exp_i : in boolean;`
341			`read_p2_i : in boolean;`
342			`read_reg_i : in boolean;`
343			`read_exp_i : in boolean;`
344			`output_pch_i : in boolean;`
345			`pch_i : in nibble_t;`
346			`p2_i : in word_t;`
347			`p2_o : out word_t;`
348			`p2l_low_imp_o : out std_logic;`
349			`p2h_low_imp_o : out std_logic`
350	4	arniml	`);`
351			`end component;`
352
353	179	arniml	`component t48_pmem_ctrl`
354	4	arniml	`port (`
355			`clk_i : in std_logic;`
356			`res_i : in std_logic;`
357			`en_clk_i : in boolean;`
358			`data_i : in word_t;`
359			`data_o : out word_t;`
360			`write_pcl_i : in boolean;`
361			`read_pcl_i : in boolean;`
362			`write_pch_i : in boolean;`
363			`read_pch_i : in boolean;`
364			`inc_pc_i : in boolean;`
365			`write_pmem_addr_i : in boolean;`
366			`addr_type_i : in pmem_addr_ident_t;`
367			`read_pmem_i : in boolean;`
368			`pmem_addr_o : out pmem_addr_t;`
369			`pmem_data_i : in word_t`
370			`);`
371			`end component;`
372
373	179	arniml	`component t48_psw`
374	4	arniml	`port (`
375			`clk_i : in std_logic;`
376			`res_i : in std_logic;`
377			`en_clk_i : in boolean;`
378			`data_i : in word_t;`
379			`data_o : out word_t;`
380			`read_psw_i : in boolean;`
381			`read_sp_i : in boolean;`
382			`write_psw_i : in boolean;`
383			`write_sp_i : in boolean;`
384			`special_data_i : in std_logic;`
385			`inc_stackp_i : in boolean;`
386			`dec_stackp_i : in boolean;`
387			`write_carry_i : in boolean;`
388			`write_aux_carry_i : in boolean;`
389			`write_f0_i : in boolean;`
390			`write_bs_i : in boolean;`
391			`carry_o : out std_logic;`
392	28	arniml	`aux_carry_i : in std_logic;`
393	4	arniml	`aux_carry_o : out std_logic;`
394			`f0_o : out std_logic;`
395			`bs_o : out std_logic`
396			`);`
397			`end component;`
398
399			`end t48_comp_pack;`

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [t48_comp_pack-p.vhd] - Blame information for rev 292