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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [t48_core_comp_pack-p.vhd] - Blame information for rev 227

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-------------------------------------------------------------------------------
--
-- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006-06-21 01:03:28 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package t48_core_comp_pack is
 
  component t48_core
    generic (
      xtal_div_3_g          : integer := 1;
      register_mnemonic_g   : integer := 1;
      include_port1_g       : integer := 1;
      include_port2_g       : integer := 1;
      include_bus_g         : integer := 1;
      include_timer_g       : integer := 1;
      sample_t1_state_g     : integer := 4
    );
 
    port (
      xtal_i        : in  std_logic;
      xtal_en_i     : in  std_logic;
      reset_i       : in  std_logic;
      t0_i          : in  std_logic;
      t0_o          : out std_logic;
      t0_dir_o      : out std_logic;
      int_n_i       : in  std_logic;
      ea_i          : in  std_logic;
      rd_n_o        : out std_logic;
      psen_n_o      : out std_logic;
      wr_n_o        : out std_logic;
      ale_o         : out std_logic;
      db_i          : in  std_logic_vector( 7 downto 0);
      db_o          : out std_logic_vector( 7 downto 0);
      db_dir_o      : out std_logic;
      t1_i          : in  std_logic;
      p2_i          : in  std_logic_vector( 7 downto 0);
      p2_o          : out std_logic_vector( 7 downto 0);
      p2l_low_imp_o : out std_logic;
      p2h_low_imp_o : out std_logic;
      p1_i          : in  std_logic_vector( 7 downto 0);
      p1_o          : out std_logic_vector( 7 downto 0);
      p1_low_imp_o  : out std_logic;
      prog_n_o      : out std_logic;
      clk_i         : in  std_logic;
      en_clk_i      : in  std_logic;
      xtal3_o       : out std_logic;
      dmem_addr_o   : out std_logic_vector( 7 downto 0);
      dmem_we_o     : out std_logic;
      dmem_data_i   : in  std_logic_vector( 7 downto 0);
      dmem_data_o   : out std_logic_vector( 7 downto 0);
      pmem_addr_o   : out std_logic_vector(11 downto 0);
      pmem_data_i   : in  std_logic_vector( 7 downto 0)
    );
  end component;
 
  component generic_ram_ena
    generic (
      addr_width_g : integer := 10;
      data_width_g : integer := 8
    );
    port (
      clk_i : in  std_logic;
      a_i   : in  std_logic_vector(addr_width_g-1 downto 0);
      we_i  : in  std_logic;
      ena_i : in  std_logic;
      d_i   : in  std_logic_vector(data_width_g-1 downto 0);
      d_o   : out std_logic_vector(data_width_g-1 downto 0)
    );
  end component;
 
  component t48_rom
    port (
      clk_i      : in  std_logic;
      rom_addr_i : in  std_logic_vector(9 downto 0);
      rom_data_o : out std_logic_vector(7 downto 0)
    );
  end component;
 
  component t49_rom
    port (
      clk_i      : in  std_logic;
      rom_addr_i : in  std_logic_vector(10 downto 0);
      rom_data_o : out std_logic_vector( 7 downto 0)
    );
  end component;
 
end t48_core_comp_pack;

Line No.	Rev	Author	Line
1	4	arniml	`-------------------------------------------------------------------------------`
2			`--`
3	227	arniml	`-- $Id: t48_core_comp_pack-p.vhd,v 1.5 2006-06-21 01:03:28 arniml Exp $`
4	4	arniml	`--`
5			`-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)`
6			`--`
7			`-- All rights reserved`
8			`--`
9			`-------------------------------------------------------------------------------`
10
11			`library ieee;`
12			`use ieee.std_logic_1164.all;`
13
14			`package t48_core_comp_pack is`
15
16			`component t48_core`
17			`generic (`
18			`xtal_div_3_g : integer := 1;`
19			`register_mnemonic_g : integer := 1;`
20			`include_port1_g : integer := 1;`
21			`include_port2_g : integer := 1;`
22			`include_bus_g : integer := 1;`
23			`include_timer_g : integer := 1;`
24			`sample_t1_state_g : integer := 4`
25			`);`
26
27			`port (`
28	209	arniml	`xtal_i : in std_logic;`
29	220	arniml	`xtal_en_i : in std_logic;`
30	209	arniml	`reset_i : in std_logic;`
31			`t0_i : in std_logic;`
32			`t0_o : out std_logic;`
33			`t0_dir_o : out std_logic;`
34			`int_n_i : in std_logic;`
35			`ea_i : in std_logic;`
36			`rd_n_o : out std_logic;`
37			`psen_n_o : out std_logic;`
38			`wr_n_o : out std_logic;`
39			`ale_o : out std_logic;`
40			`db_i : in std_logic_vector( 7 downto 0);`
41			`db_o : out std_logic_vector( 7 downto 0);`
42			`db_dir_o : out std_logic;`
43			`t1_i : in std_logic;`
44			`p2_i : in std_logic_vector( 7 downto 0);`
45			`p2_o : out std_logic_vector( 7 downto 0);`
46			`p2l_low_imp_o : out std_logic;`
47			`p2h_low_imp_o : out std_logic;`
48			`p1_i : in std_logic_vector( 7 downto 0);`
49			`p1_o : out std_logic_vector( 7 downto 0);`
50			`p1_low_imp_o : out std_logic;`
51			`prog_n_o : out std_logic;`
52			`clk_i : in std_logic;`
53			`en_clk_i : in std_logic;`
54			`xtal3_o : out std_logic;`
55			`dmem_addr_o : out std_logic_vector( 7 downto 0);`
56			`dmem_we_o : out std_logic;`
57			`dmem_data_i : in std_logic_vector( 7 downto 0);`
58			`dmem_data_o : out std_logic_vector( 7 downto 0);`
59			`pmem_addr_o : out std_logic_vector(11 downto 0);`
60			`pmem_data_i : in std_logic_vector( 7 downto 0)`
61	4	arniml	`);`
62			`end component;`
63
64	227	arniml	`component generic_ram_ena`
65	4	arniml	`generic (`
66	227	arniml	`addr_width_g : integer := 10;`
67			`data_width_g : integer := 8`
68	4	arniml	`);`
69			`port (`
70	227	arniml	`clk_i : in std_logic;`
71			`a_i : in std_logic_vector(addr_width_g-1 downto 0);`
72			`we_i : in std_logic;`
73			`ena_i : in std_logic;`
74			`d_i : in std_logic_vector(data_width_g-1 downto 0);`
75			`d_o : out std_logic_vector(data_width_g-1 downto 0)`
76			`);`
77			`end component;`
78
79			`component t48_rom`
80			`port (`
81	4	arniml	`clk_i : in std_logic;`
82	227	arniml	`rom_addr_i : in std_logic_vector(9 downto 0);`
83	4	arniml	`rom_data_o : out std_logic_vector(7 downto 0)`
84			`);`
85			`end component;`
86
87	227	arniml	`component t49_rom`
88	4	arniml	`port (`
89			`clk_i : in std_logic;`
90	227	arniml	`rom_addr_i : in std_logic_vector(10 downto 0);`
91			`rom_data_o : out std_logic_vector( 7 downto 0)`
92	4	arniml	`);`
93			`end component;`
94
95			`end t48_core_comp_pack;`

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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [t48_core_comp_pack-p.vhd] - Blame information for rev 227