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[/] [t48/] [tags/] [rel_1_0/] [sim/] [rtl_sim/] [Makefile.hier] - Blame information for rev 232

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##############################################################################
#
# Core Makefile for the T48 project.
#
# The dependencies for all VHDL source files are stored here.
# Include this file from within the tool-specific Makefile. See
# Makefile.ghdl for an example how to use it.
#
# The following environment/make variables are expected. Set them in the
# tool-specific Makefile or from the shell.
#
#  PROJECT_DIR : Project base directory
#                Set in sw/init_project.sh
#
#  LIB_WORK    : object directory for the work library
#                /t48/sim/rtl_sim/
#
#  MAKE_LIB    : command to create the work library
#
#  ANALYZE     : command calling the tool-specific compiler for analysis of
#                the VHDL code
#
#  CLEAN       : command to clean the tool-object directory
#
#  Various VHDL design units.
#
#
# Copyright (c) 2004-2006, Arnim Laeuger (arniml@opencores.org)
#
# All rights reserved
#
##############################################################################
 
RTL_DIR   = $(PROJECT_DIR)/rtl/vhdl
BENCH_DIR = $(PROJECT_DIR)/bench/vhdl
 
 
$(LIB_WORK):
        $(MAKE_LIB)
 
.PHONY: clean
clean:
        $(CLEAN); \
        rm -rf *~
 
.PHONY: analyze
analyze: $(LIB_WORK) $(tb_behav_c0) $(tb_t8048_behav_c0)
 
 
$(alu) : $(RTL_DIR)/alu.vhd   \
                $(alu_pack)   \
                $(t48_pack)   \
                $(t48_tb_pack)
        $(ANALYZE) $<
 
$(alu_pack) : $(RTL_DIR)/alu_pack-p.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(alu_rtl_c0) : $(RTL_DIR)/alu-c.vhd \
                $(alu)
        $(ANALYZE) $<
 
$(bus_mux) : $(RTL_DIR)/bus_mux.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(bus_mux_rtl_c0) : $(RTL_DIR)/bus_mux-c.vhd \
                $(bus_mux-rtl)               \
                $(bus_mux)
        $(ANALYZE) $<
 
$(clock_ctrl) : $(RTL_DIR)/clock_ctrl.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(clock_ctrl_rtl_c0) : $(RTL_DIR)/clock_ctrl-c.vhd \
                $(clock_ctrl)
        $(ANALYZE) $<
 
$(cond_branch) : $(RTL_DIR)/cond_branch.vhd \
                $(cond_branch_pack)         \
                $(t48_pack)
        $(ANALYZE) $<
 
$(cond_branch_pack) : $(RTL_DIR)/cond_branch_pack-p.vhd
        $(ANALYZE) $<
 
$(cond_branch_rtl_c0) : $(RTL_DIR)/cond_branch-c.vhd \
                $(cond_branch)
        $(ANALYZE) $<
 
$(db_bus) : $(RTL_DIR)/db_bus.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(db_bus_rtl_c0) : $(RTL_DIR)/db_bus-c.vhd \
                $(db_bus)
        $(ANALYZE) $<
 
$(decoder) : $(RTL_DIR)/decoder.vhd \
                $(pmem_ctrl_pack)   \
                $(dmem_ctrl_pack)   \
                $(cond_branch_pack) \
                $(alu_pack)         \
                $(t48_pack)         \
                $(t48_comp_pack)    \
                $(t48_tb_pack)      \
                $(decoder_pack)
        $(ANALYZE) $<
 
$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd
        $(ANALYZE) $<
 
$(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \
                $(opc_decoder_rtl_c0)        \
                $(int_rtl_c0)                \
                $(decoder)
        $(ANALYZE) $<
 
$(dmem_ctrl) : $(RTL_DIR)/dmem_ctrl.vhd \
                $(dmem_ctrl_pack)       \
                $(t48_pack)
        $(ANALYZE) $<
 
$(dmem_ctrl_pack) : $(RTL_DIR)/dmem_ctrl_pack-p.vhd
        $(ANALYZE) $<
 
$(dmem_ctrl_rtl_c0) : $(RTL_DIR)/dmem_ctrl-c.vhd \
                $(dmem_ctrl)
        $(ANALYZE) $<
 
$(int) : $(RTL_DIR)/int.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(int_rtl_c0) : $(RTL_DIR)/int-c.vhd \
                $(int)
        $(ANALYZE) $<
 
$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \
                $(decoder_pack)             \
                $(t48_pack)                 \
                $(pmem_ctrl_pack)           \
                $(dmem_ctrl_pack)           \
                $(cond_branch_pack)         \
                $(alu_pack)                 \
                $(t48_comp_pack)
        $(ANALYZE) $<
 
$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \
                $(opc_table_rtl_c0) \
                $(opc_decoder)
        $(ANALYZE) $<
 
$(opc_table) : $(RTL_DIR)/opc_table.vhd \
                $(decoder_pack)         \
                $(t48_pack)
        $(ANALYZE) $<
 
$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \
                $(opc_table)
        $(ANALYZE) $<
 
$(p1) : $(RTL_DIR)/p1.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(p1_rtl_c0) : $(RTL_DIR)/p1-c.vhd \
                $(p1)
        $(ANALYZE) $<
 
$(p2) : $(RTL_DIR)/p2.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(p2_rtl_c0) : $(RTL_DIR)/p2-c.vhd \
                $(p2)
        $(ANALYZE) $<
 
$(pmem_ctrl) : $(RTL_DIR)/pmem_ctrl.vhd \
                $(pmem_ctrl_pack)       \
                $(t48_pack)
        $(ANALYZE) $<
 
$(pmem_ctrl_pack) : $(RTL_DIR)/pmem_ctrl_pack-p.vhd
        $(ANALYZE) $<
 
$(pmem_ctrl_rtl_c0) : $(RTL_DIR)/pmem_ctrl-c.vhd \
                $(pmem_ctrl)
        $(ANALYZE) $<
 
$(psw) : $(RTL_DIR)/psw.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(psw_rtl_c0) : $(RTL_DIR)/psw-c.vhd \
                $(psw)
        $(ANALYZE) $<
 
$(lpm_ram_dq) : $(RTL_DIR)/system/lpm_ram_dq.vhd
        $(ANALYZE) $<
 
$(generic_ram_ena) : $(RTL_DIR)/system/generic_ram_ena.vhd
        $(ANALYZE) $<
$(generic_ram_ena_rtl_c0) : $(RTL_DIR)/system/generic_ram_ena-c.vhd \
                            $(generic_ram_ena)
        $(ANALYZE) $<
 
$(lpm_rom) : $(RTL_DIR)/system/lpm_rom.vhd
        $(ANALYZE) $<
 
$(t48_rom) : $(RTL_DIR)/system/t48_rom-e.vhd
        $(ANALYZE) $<
$(t48_rom_lpm_a) : $(BENCH_DIR)/t48_rom-lpm-a.vhd \
                   $(t48_rom)
        $(ANALYZE) $<
$(t48_rom_lpm_c0) : $(BENCH_DIR)/t48_rom-lpm-c.vhd \
                    $(lpm_rom)                     \
                    $(t48_rom_lpm_a)
        $(ANALYZE) $<
 
$(t49_rom) : $(RTL_DIR)/system/t49_rom-e.vhd
        $(ANALYZE) $<
$(t49_rom_lpm_a) : $(BENCH_DIR)/t49_rom-lpm-a.vhd \
                   $(t49_rom)
        $(ANALYZE) $<
$(t49_rom_lpm_c0) : $(BENCH_DIR)/t49_rom-lpm-c.vhd \
                    $(lpm_rom)                     \
                    $(t49_rom_lpm_a)
        $(ANALYZE) $<
 
$(t48_comp_pack) : $(RTL_DIR)/t48_comp_pack-p.vhd \
                $(pmem_ctrl_pack)                 \
                $(dmem_ctrl_pack)                 \
                $(decoder_pack)                   \
                $(cond_branch_pack)               \
                $(t48_pack)                       \
                $(alu_pack)
        $(ANALYZE) $<
 
$(t48_core) : $(RTL_DIR)/t48_core.vhd \
                $(decoder_pack)       \
                $(t48_comp_pack)      \
                $(pmem_ctrl_pack)     \
                $(dmem_ctrl_pack)     \
                $(cond_branch_pack)   \
                $(t48_pack)           \
                $(alu_pack)
        $(ANALYZE) $<
 
$(t48_core_comp_pack) : $(RTL_DIR)/t48_core_comp_pack-p.vhd
        $(ANALYZE) $<
 
$(t48_core_struct_c0) : $(RTL_DIR)/t48_core-c.vhd \
                $(psw_rtl_c0)                     \
                $(pmem_ctrl_rtl_c0)               \
                $(p2_rtl_c0)                      \
                $(p1_rtl_c0)                      \
                $(timer_rtl_c0)                   \
                $(dmem_ctrl_rtl_c0)               \
                $(decoder_rtl_c0)                 \
                $(db_bus_rtl_c0)                  \
                $(cond_branch_rtl_c0)             \
                $(clock_ctrl_rtl_c0)              \
                $(bus_mux_rtl_c0)                 \
                $(alu_rtl_c0)                     \
                $(decoder_pack)                   \
                $(t48_comp_pack)                  \
                $(pmem_ctrl_pack)                 \
                $(dmem_ctrl_pack)                 \
                $(cond_branch_pack)               \
                $(t48_pack)                       \
                $(alu_pack)                       \
                $(t48_core-struct)                \
                $(t48_core)
        $(ANALYZE) $<
 
$(t48_pack) : $(RTL_DIR)/t48_pack-p.vhd
        $(ANALYZE) $<
 
$(t48_tb_pack) : $(RTL_DIR)/t48_tb_pack-p.vhd
        $(ANALYZE) $<
 
$(t8048_notri) : $(RTL_DIR)/system/t8048_notri.vhd \
                $(t48_core_comp_pack)
        $(ANALYZE) $<
 
$(t8048_notri_struct_c0) : $(RTL_DIR)/system/t8048_notri-c.vhd \
                $(t48_core_struct_c0)                          \
                $(generic_ram_ena_rtl_c0)                      \
                $(t48_rom_lpm_c0)                              \
                $(t48_core_comp_pack)                          \
                $(t8048_notri)
        $(ANALYZE) $<
 
$(t48_system_comp_pack) : $(RTL_DIR)/system/t48_system_comp_pack-p.vhd
        $(ANALYZE) $<
 
$(t8048) : $(RTL_DIR)/system/t8048.vhd \
                $(t48_system_comp_pack)
        $(ANALYZE) $<
 
$(t8048_struct_c0) : $(RTL_DIR)/system/t8048-c.vhd \
                $(t8048_notri_struct_c0)           \
                $(t8048)
        $(ANALYZE) $<
 
$(t8039_notri) : $(RTL_DIR)/system/t8039_notri.vhd \
                $(t48_core_comp_pack)
        $(ANALYZE) $<
 
$(t8039_notri_struct_c0) : $(RTL_DIR)/system/t8039_notri-c.vhd \
                $(t48_core_struct_c0)                          \
                $(generic_ram_ena_rtl_c0)                      \
                $(t8039_notri)
        $(ANALYZE) $<
 
$(t8039) : $(RTL_DIR)/system/t8039.vhd \
                $(t48_system_comp_pack)
        $(ANALYZE) $<
 
$(t8039_struct_c0) : $(RTL_DIR)/system/t8039-c.vhd \
                $(t8039_notri_struct_c0)           \
                $(t8039)
        $(ANALYZE) $<
 
$(if_timing) : $(BENCH_DIR)/if_timing.vhd
        $(ANALYZE) $<
 
$(if_timing_behav_c0) : $(BENCH_DIR)/if_timing-c.vhd \
                $(if_timing)
        $(ANALYZE) $<
 
$(tb) : $(BENCH_DIR)/tb.vhd           \
                $(t48_tb_pack)        \
                $(t48_core_comp_pack)
        $(ANALYZE) $<
 
$(tb_behav_c0) : $(BENCH_DIR)/tb-c.vhd    \
                $(if_timing_behav_c0)     \
                $(t48_core_struct_c0)     \
                $(generic_ram_ena_rtl_c0) \
                $(lpm_rom)                \
                $(t48_tb_pack)            \
                $(t48_core_comp_pack)     \
                $(tb-behav)               \
                $(tb)
        $(ANALYZE) $<
 
$(tb_t8039) : $(BENCH_DIR)/tb_t8039.vhd \
                $(t48_tb_pack)          \
                $(t48_core_comp_pack)
        $(ANALYZE) $<
 
$(tb_t8039_behav_c0) : $(BENCH_DIR)/tb_t8039-c.vhd \
                $(t8039_struct_c0)                 \
                $(generic_ram_rtl_c0)              \
                $(lpm_rom)                         \
                $(t48_tb_pack)                     \
                $(t48_core_comp_pack)              \
                $(t48_system_comp_pack)            \
                $(tb_t8039)
        $(ANALYZE) $<
 
$(tb_t8048) : $(BENCH_DIR)/tb_t8048.vhd \
                $(t48_tb_pack)          \
                $(t48_core_comp_pack)
        $(ANALYZE) $<
 
$(tb_t8048_behav_c0) : $(BENCH_DIR)/tb_t8048-c.vhd \
                $(t8048_struct_c0)                 \
                $(generic_ram_ena_rtl_c0)          \
                $(t48_tb_pack)                     \
                $(t48_core_comp_pack)              \
                $(tb_t8048)
        $(ANALYZE) $<
 
$(timer) : $(RTL_DIR)/timer.vhd \
                $(t48_pack)
        $(ANALYZE) $<
 
$(timer_rtl_c0) : $(RTL_DIR)/timer-c.vhd \
                $(timer-rtl)             \
                $(t48_pack)              \
                $(timer)
        $(ANALYZE) $<

Line No.	Rev	Author	Line
1	11	arniml	`##############################################################################`
2			`#`
3			`# Core Makefile for the T48 project.`
4			`#`
5			`# The dependencies for all VHDL source files are stored here.`
6			`# Include this file from within the tool-specific Makefile. See`
7			`# Makefile.ghdl for an example how to use it.`
8			`#`
9			`# The following environment/make variables are expected. Set them in the`
10			`# tool-specific Makefile or from the shell.`
11			`#`
12	31	arniml	`# PROJECT_DIR : Project base directory`
13			`# Set in sw/init_project.sh`
14	11	arniml	`#`
15	31	arniml	`# LIB_WORK : object directory for the work library`
16			`# /t48/sim/rtl_sim/`
17	11	arniml	`#`
18	31	arniml	`# MAKE_LIB : command to create the work library`
19	11	arniml	`#`
20	31	arniml	`# ANALYZE : command calling the tool-specific compiler for analysis of`
21			`# the VHDL code`
22	11	arniml	`#`
23	31	arniml	`# CLEAN : command to clean the tool-object directory`
24	11	arniml	`#`
25			`# Various VHDL design units.`
26			`#`
27			`#`
28	218	arniml	`# Copyright (c) 2004-2006, Arnim Laeuger (arniml@opencores.org)`
29	11	arniml	`#`
30			`# All rights reserved`
31			`#`
32			`##############################################################################`
33	9	arniml
34	31	arniml	`RTL_DIR = $(PROJECT_DIR)/rtl/vhdl`
35			`BENCH_DIR = $(PROJECT_DIR)/bench/vhdl`
36	9	arniml
37
38			`$(LIB_WORK):`
39			`$(MAKE_LIB)`
40
41			`.PHONY: clean`
42			`clean:`
43			`$(CLEAN); \`
44	71	arniml	`rm -rf *~`
45	9	arniml
46			`.PHONY: analyze`
47			`analyze: $(LIB_WORK) $(tb_behav_c0) $(tb_t8048_behav_c0)`
48
49
50	232	arniml	`$(alu) : $(RTL_DIR)/alu.vhd \`
51			`$(alu_pack) \`
52			`$(t48_pack) \`
53	9	arniml	`$(t48_tb_pack)`
54	218	arniml	`$(ANALYZE) $<`
55	9	arniml
56			`$(alu_pack) : $(RTL_DIR)/alu_pack-p.vhd \`
57			`$(t48_pack)`
58	218	arniml	`$(ANALYZE) $<`
59	9	arniml
60			`$(alu_rtl_c0) : $(RTL_DIR)/alu-c.vhd \`
61			`$(alu)`
62	218	arniml	`$(ANALYZE) $<`
63	9	arniml
64			`$(bus_mux) : $(RTL_DIR)/bus_mux.vhd \`
65			`$(t48_pack)`
66	218	arniml	`$(ANALYZE) $<`
67	9	arniml
68			`$(bus_mux_rtl_c0) : $(RTL_DIR)/bus_mux-c.vhd \`
69	232	arniml	`$(bus_mux-rtl) \`
70	9	arniml	`$(bus_mux)`
71	218	arniml	`$(ANALYZE) $<`
72	9	arniml
73			`$(clock_ctrl) : $(RTL_DIR)/clock_ctrl.vhd \`
74			`$(t48_pack)`
75	218	arniml	`$(ANALYZE) $<`
76	9	arniml
77			`$(clock_ctrl_rtl_c0) : $(RTL_DIR)/clock_ctrl-c.vhd \`
78			`$(clock_ctrl)`
79	218	arniml	`$(ANALYZE) $<`
80	9	arniml
81			`$(cond_branch) : $(RTL_DIR)/cond_branch.vhd \`
82	232	arniml	`$(cond_branch_pack) \`
83	9	arniml	`$(t48_pack)`
84	218	arniml	`$(ANALYZE) $<`
85	9	arniml
86			`$(cond_branch_pack) : $(RTL_DIR)/cond_branch_pack-p.vhd`
87	218	arniml	`$(ANALYZE) $<`
88	9	arniml
89			`$(cond_branch_rtl_c0) : $(RTL_DIR)/cond_branch-c.vhd \`
90			`$(cond_branch)`
91	218	arniml	`$(ANALYZE) $<`
92	9	arniml
93			`$(db_bus) : $(RTL_DIR)/db_bus.vhd \`
94			`$(t48_pack)`
95	218	arniml	`$(ANALYZE) $<`
96	9	arniml
97			`$(db_bus_rtl_c0) : $(RTL_DIR)/db_bus-c.vhd \`
98			`$(db_bus)`
99	218	arniml	`$(ANALYZE) $<`
100	9	arniml
101			`$(decoder) : $(RTL_DIR)/decoder.vhd \`
102	232	arniml	`$(pmem_ctrl_pack) \`
103			`$(dmem_ctrl_pack) \`
104	9	arniml	`$(cond_branch_pack) \`
105	232	arniml	`$(alu_pack) \`
106			`$(t48_pack) \`
107			`$(t48_comp_pack) \`
108			`$(t48_tb_pack) \`
109	9	arniml	`$(decoder_pack)`
110	218	arniml	`$(ANALYZE) $<`
111	9	arniml
112			`$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd`
113	218	arniml	`$(ANALYZE) $<`
114	9	arniml
115			`$(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \`
116	232	arniml	`$(opc_decoder_rtl_c0) \`
117			`$(int_rtl_c0) \`
118	9	arniml	`$(decoder)`
119	218	arniml	`$(ANALYZE) $<`
120	9	arniml
121			`$(dmem_ctrl) : $(RTL_DIR)/dmem_ctrl.vhd \`
122	232	arniml	`$(dmem_ctrl_pack) \`
123	9	arniml	`$(t48_pack)`
124	218	arniml	`$(ANALYZE) $<`
125	9	arniml
126			`$(dmem_ctrl_pack) : $(RTL_DIR)/dmem_ctrl_pack-p.vhd`
127	218	arniml	`$(ANALYZE) $<`
128	9	arniml
129			`$(dmem_ctrl_rtl_c0) : $(RTL_DIR)/dmem_ctrl-c.vhd \`
130			`$(dmem_ctrl)`
131	218	arniml	`$(ANALYZE) $<`
132	9	arniml
133			`$(int) : $(RTL_DIR)/int.vhd \`
134			`$(t48_pack)`
135	218	arniml	`$(ANALYZE) $<`
136	9	arniml
137			`$(int_rtl_c0) : $(RTL_DIR)/int-c.vhd \`
138			`$(int)`
139	218	arniml	`$(ANALYZE) $<`
140	9	arniml
141			`$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \`
142	232	arniml	`$(decoder_pack) \`
143			`$(t48_pack) \`
144			`$(pmem_ctrl_pack) \`
145			`$(dmem_ctrl_pack) \`
146			`$(cond_branch_pack) \`
147			`$(alu_pack) \`
148	9	arniml	`$(t48_comp_pack)`
149	218	arniml	`$(ANALYZE) $<`
150	9	arniml
151			`$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \`
152			`$(opc_table_rtl_c0) \`
153			`$(opc_decoder)`
154	218	arniml	`$(ANALYZE) $<`
155	9	arniml
156			`$(opc_table) : $(RTL_DIR)/opc_table.vhd \`
157	232	arniml	`$(decoder_pack) \`
158	9	arniml	`$(t48_pack)`
159	218	arniml	`$(ANALYZE) $<`
160	9	arniml
161			`$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \`
162			`$(opc_table)`
163	218	arniml	`$(ANALYZE) $<`
164	9	arniml
165			`$(p1) : $(RTL_DIR)/p1.vhd \`
166			`$(t48_pack)`
167	218	arniml	`$(ANALYZE) $<`
168	9	arniml
169			`$(p1_rtl_c0) : $(RTL_DIR)/p1-c.vhd \`
170			`$(p1)`
171	218	arniml	`$(ANALYZE) $<`
172	9	arniml
173			`$(p2) : $(RTL_DIR)/p2.vhd \`
174			`$(t48_pack)`
175	218	arniml	`$(ANALYZE) $<`
176	9	arniml
177			`$(p2_rtl_c0) : $(RTL_DIR)/p2-c.vhd \`
178			`$(p2)`
179	218	arniml	`$(ANALYZE) $<`
180	9	arniml
181			`$(pmem_ctrl) : $(RTL_DIR)/pmem_ctrl.vhd \`
182	232	arniml	`$(pmem_ctrl_pack) \`
183	9	arniml	`$(t48_pack)`
184	218	arniml	`$(ANALYZE) $<`
185	9	arniml
186			`$(pmem_ctrl_pack) : $(RTL_DIR)/pmem_ctrl_pack-p.vhd`
187	218	arniml	`$(ANALYZE) $<`
188	9	arniml
189			`$(pmem_ctrl_rtl_c0) : $(RTL_DIR)/pmem_ctrl-c.vhd \`
190			`$(pmem_ctrl)`
191	218	arniml	`$(ANALYZE) $<`
192	9	arniml
193			`$(psw) : $(RTL_DIR)/psw.vhd \`
194			`$(t48_pack)`
195	218	arniml	`$(ANALYZE) $<`
196	9	arniml
197			`$(psw_rtl_c0) : $(RTL_DIR)/psw-c.vhd \`
198			`$(psw)`
199	218	arniml	`$(ANALYZE) $<`
200	9	arniml
201	232	arniml	`$(lpm_ram_dq) : $(RTL_DIR)/system/lpm_ram_dq.vhd`
202	218	arniml	`$(ANALYZE) $<`
203	9	arniml
204	232	arniml	`$(generic_ram_ena) : $(RTL_DIR)/system/generic_ram_ena.vhd`
205	218	arniml	`$(ANALYZE) $<`
206	232	arniml	`$(generic_ram_ena_rtl_c0) : $(RTL_DIR)/system/generic_ram_ena-c.vhd \`
207			`$(generic_ram_ena)`
208	218	arniml	`$(ANALYZE) $<`
209	9	arniml
210	232	arniml	`$(lpm_rom) : $(RTL_DIR)/system/lpm_rom.vhd`
211	218	arniml	`$(ANALYZE) $<`
212	9	arniml
213	232	arniml	`$(t48_rom) : $(RTL_DIR)/system/t48_rom-e.vhd`
214	218	arniml	`$(ANALYZE) $<`
215	232	arniml	`$(t48_rom_lpm_a) : $(BENCH_DIR)/t48_rom-lpm-a.vhd \`
216			`$(t48_rom)`
217			`$(ANALYZE) $<`
218			`$(t48_rom_lpm_c0) : $(BENCH_DIR)/t48_rom-lpm-c.vhd \`
219			`$(lpm_rom) \`
220			`$(t48_rom_lpm_a)`
221			`$(ANALYZE) $<`
222	9	arniml
223	232	arniml	`$(t49_rom) : $(RTL_DIR)/system/t49_rom-e.vhd`
224	218	arniml	`$(ANALYZE) $<`
225	232	arniml	`$(t49_rom_lpm_a) : $(BENCH_DIR)/t49_rom-lpm-a.vhd \`
226			`$(t49_rom)`
227			`$(ANALYZE) $<`
228			`$(t49_rom_lpm_c0) : $(BENCH_DIR)/t49_rom-lpm-c.vhd \`
229			`$(lpm_rom) \`
230			`$(t49_rom_lpm_a)`
231			`$(ANALYZE) $<`
232	9	arniml
233			`$(t48_comp_pack) : $(RTL_DIR)/t48_comp_pack-p.vhd \`
234	232	arniml	`$(pmem_ctrl_pack) \`
235			`$(dmem_ctrl_pack) \`
236			`$(decoder_pack) \`
237			`$(cond_branch_pack) \`
238			`$(t48_pack) \`
239	9	arniml	`$(alu_pack)`
240	218	arniml	`$(ANALYZE) $<`
241	9	arniml
242			`$(t48_core) : $(RTL_DIR)/t48_core.vhd \`
243	232	arniml	`$(decoder_pack) \`
244			`$(t48_comp_pack) \`
245			`$(pmem_ctrl_pack) \`
246			`$(dmem_ctrl_pack) \`
247			`$(cond_branch_pack) \`
248			`$(t48_pack) \`
249	9	arniml	`$(alu_pack)`
250	218	arniml	`$(ANALYZE) $<`
251	9	arniml
252			`$(t48_core_comp_pack) : $(RTL_DIR)/t48_core_comp_pack-p.vhd`
253	218	arniml	`$(ANALYZE) $<`
254	9	arniml
255			`$(t48_core_struct_c0) : $(RTL_DIR)/t48_core-c.vhd \`
256	232	arniml	`$(psw_rtl_c0) \`
257			`$(pmem_ctrl_rtl_c0) \`
258			`$(p2_rtl_c0) \`
259			`$(p1_rtl_c0) \`
260			`$(timer_rtl_c0) \`
261			`$(dmem_ctrl_rtl_c0) \`
262			`$(decoder_rtl_c0) \`
263			`$(db_bus_rtl_c0) \`
264			`$(cond_branch_rtl_c0) \`
265			`$(clock_ctrl_rtl_c0) \`
266			`$(bus_mux_rtl_c0) \`
267			`$(alu_rtl_c0) \`
268			`$(decoder_pack) \`
269			`$(t48_comp_pack) \`
270			`$(pmem_ctrl_pack) \`
271			`$(dmem_ctrl_pack) \`
272			`$(cond_branch_pack) \`
273			`$(t48_pack) \`
274			`$(alu_pack) \`
275			`$(t48_core-struct) \`
276	9	arniml	`$(t48_core)`
277	218	arniml	`$(ANALYZE) $<`
278	9	arniml
279			`$(t48_pack) : $(RTL_DIR)/t48_pack-p.vhd`
280	218	arniml	`$(ANALYZE) $<`
281	9	arniml
282			`$(t48_tb_pack) : $(RTL_DIR)/t48_tb_pack-p.vhd`
283	218	arniml	`$(ANALYZE) $<`
284	9	arniml
285	151	arniml	`$(t8048_notri) : $(RTL_DIR)/system/t8048_notri.vhd \`
286	9	arniml	`$(t48_core_comp_pack)`
287	218	arniml	`$(ANALYZE) $<`
288	9	arniml
289	151	arniml	`$(t8048_notri_struct_c0) : $(RTL_DIR)/system/t8048_notri-c.vhd \`
290	232	arniml	`$(t48_core_struct_c0) \`
291			`$(generic_ram_ena_rtl_c0) \`
292			`$(t48_rom_lpm_c0) \`
293			`$(t48_core_comp_pack) \`
294	151	arniml	`$(t8048_notri)`
295	218	arniml	`$(ANALYZE) $<`
296	151	arniml
297			`$(t48_system_comp_pack) : $(RTL_DIR)/system/t48_system_comp_pack-p.vhd`
298	218	arniml	`$(ANALYZE) $<`
299	151	arniml
300			`$(t8048) : $(RTL_DIR)/system/t8048.vhd \`
301			`$(t48_system_comp_pack)`
302	218	arniml	`$(ANALYZE) $<`
303	151	arniml
304			`$(t8048_struct_c0) : $(RTL_DIR)/system/t8048-c.vhd \`
305	232	arniml	`$(t8048_notri_struct_c0) \`
306	9	arniml	`$(t8048)`
307	218	arniml	`$(ANALYZE) $<`
308	9	arniml
309	154	arniml	`$(t8039_notri) : $(RTL_DIR)/system/t8039_notri.vhd \`
310			`$(t48_core_comp_pack)`
311	218	arniml	`$(ANALYZE) $<`
312	154	arniml
313			`$(t8039_notri_struct_c0) : $(RTL_DIR)/system/t8039_notri-c.vhd \`
314	232	arniml	`$(t48_core_struct_c0) \`
315			`$(generic_ram_ena_rtl_c0) \`
316	154	arniml	`$(t8039_notri)`
317	218	arniml	`$(ANALYZE) $<`
318	154	arniml
319	71	arniml	`$(t8039) : $(RTL_DIR)/system/t8039.vhd \`
320	198	arniml	`$(t48_system_comp_pack)`
321	218	arniml	`$(ANALYZE) $<`
322	71	arniml
323			`$(t8039_struct_c0) : $(RTL_DIR)/system/t8039-c.vhd \`
324	232	arniml	`$(t8039_notri_struct_c0) \`
325	71	arniml	`$(t8039)`
326	218	arniml	`$(ANALYZE) $<`
327	71	arniml
328	79	arniml	`$(if_timing) : $(BENCH_DIR)/if_timing.vhd`
329	218	arniml	`$(ANALYZE) $<`
330	79	arniml
331			`$(if_timing_behav_c0) : $(BENCH_DIR)/if_timing-c.vhd \`
332			`$(if_timing)`
333	218	arniml	`$(ANALYZE) $<`
334	79	arniml
335	232	arniml	`$(tb) : $(BENCH_DIR)/tb.vhd \`
336			`$(t48_tb_pack) \`
337	9	arniml	`$(t48_core_comp_pack)`
338	218	arniml	`$(ANALYZE) $<`
339	9	arniml
340	232	arniml	`$(tb_behav_c0) : $(BENCH_DIR)/tb-c.vhd \`
341			`$(if_timing_behav_c0) \`
342			`$(t48_core_struct_c0) \`
343			`$(generic_ram_ena_rtl_c0) \`
344			`$(lpm_rom) \`
345			`$(t48_tb_pack) \`
346			`$(t48_core_comp_pack) \`
347			`$(tb-behav) \`
348	9	arniml	`$(tb)`
349	218	arniml	`$(ANALYZE) $<`
350	9	arniml
351	71	arniml	`$(tb_t8039) : $(BENCH_DIR)/tb_t8039.vhd \`
352	232	arniml	`$(t48_tb_pack) \`
353	71	arniml	`$(t48_core_comp_pack)`
354	218	arniml	`$(ANALYZE) $<`
355	71	arniml
356			`$(tb_t8039_behav_c0) : $(BENCH_DIR)/tb_t8039-c.vhd \`
357	232	arniml	`$(t8039_struct_c0) \`
358			`$(generic_ram_rtl_c0) \`
359			`$(lpm_rom) \`
360			`$(t48_tb_pack) \`
361			`$(t48_core_comp_pack) \`
362			`$(t48_system_comp_pack) \`
363	71	arniml	`$(tb_t8039)`
364	218	arniml	`$(ANALYZE) $<`
365	71	arniml
366	9	arniml	`$(tb_t8048) : $(BENCH_DIR)/tb_t8048.vhd \`
367	232	arniml	`$(t48_tb_pack) \`
368	9	arniml	`$(t48_core_comp_pack)`
369	218	arniml	`$(ANALYZE) $<`
370	9	arniml
371			`$(tb_t8048_behav_c0) : $(BENCH_DIR)/tb_t8048-c.vhd \`
372	232	arniml	`$(t8048_struct_c0) \`
373			`$(generic_ram_ena_rtl_c0) \`
374			`$(t48_tb_pack) \`
375			`$(t48_core_comp_pack) \`
376	9	arniml	`$(tb_t8048)`
377	218	arniml	`$(ANALYZE) $<`
378	9	arniml
379			`$(timer) : $(RTL_DIR)/timer.vhd \`
380			`$(t48_pack)`
381	218	arniml	`$(ANALYZE) $<`
382	9	arniml
383			`$(timer_rtl_c0) : $(RTL_DIR)/timer-c.vhd \`
384	232	arniml	`$(timer-rtl) \`
385			`$(t48_pack) \`
386	9	arniml	`$(timer)`
387	218	arniml	`$(ANALYZE) $<`

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[/] [t48/] [tags/] [rel_1_0/] [sim/] [rtl_sim/] [Makefile.hier] - Blame information for rev 232