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README for the T48 uController project
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======================================
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Version: $Date: 2008-04-30 22:32:11 $
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$Name: not supported by cvs2svn $
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Introduction
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------------
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The T48 µController core is an implementation of the MCS-48 microcontroller
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family architecture. While being a controller core for SoC, it also aims for
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code-compatability and cycle-accuracy so that it can be used as a drop-in
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replacement for any MCS-48 controller.
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It can be configured to better suit the requirements and characteristics of
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the integrating system. On the other hand, nearly the full functionality of a
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stock 8048/8049 is available.
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Download
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--------
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Download the latest stable release from the project homepage at OpenCores.org:
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http://www.opencores.org/projects.cgi/web/t48/overview/
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You can get the latest version of the design files from CVS:
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http://www.opencores.org/pdownloads.cgi/list/t48
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Please keep in mind that this is work in progress and might contain smaller or
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bigger problems.
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You should also check the Tracker for known bugs and see if they affect your
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work.
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Installation
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------------
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Once the directory structure is generated either by check-out from CVS or by
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unpacking the tar-archive, the central project initialization file should be
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set up. A template called init_project.template.sh is located in the sw
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directory where a copy can be edited. Normally, only the definition for the
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variable PROJECT_DIR has to be adjusted to the path where the directory
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structure is located.
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The commands for setting the necessary variables assume a bash/sh-like
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shell. In case you run a different shell like csh or ksh, you should adjust
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these commands as well.
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The meaning of the variables is as follows:
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* PROJECT_DIR
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Points to the root of the project installation. All further references are
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derived from its setting.
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* VERIF_DIR
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Location of the verification suite.
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* SIM_DIR
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Directory for running simulations.
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These variables must be properly set whenever scripts or makefiles of the T48
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project are executed. Otherwise, you will most likely encounter error
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messages.
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NOTE: The concepts of the mentioned shells require that the init_project.sh is
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run in the context of the shell. I.e. you should 'source' the script
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instead of executing it like a command. This will make sure that the
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variable settings are really effective in the calling shell instance.
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Directory Structure
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-------------------
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The project's directory structure follows the proposal of OpenCores.org.
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t48
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\--+-- rtl
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| \-- vhdl : VHDL code containing the RTL description
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| +-- system : RTL VHDL code of sample systems.
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| \-- t8243 : RTL VHDL code of 8243 core.
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+-- bench
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| \-- vhdl : VHDL testbench code.
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+-- sim
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| \-- rtl_sim : Directory for running simulations.
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+-- syn
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| \-- t8048 : T8048 toplevel example synthesis.
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| +-- b5x300 : for SpartanIIe 300.
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| \-- jopcyc : for Cyclone EP1C12.
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\-- sw : General purpose scripts and files.
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+-- i8039emu : An MCS-48 emulator written in C.
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\-- verif : The verification suite.
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+-- include : Global includes and makefiles.
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+-- black_box : Black-box verification tests.
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+-- white_box : White-box verification tests.
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\-- gp_sw : General purpose software.
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Compiling the VHDL Code
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-----------------------
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VHDL compilation and simulation tasks take place inside in sim/rtl_sim
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directory. The project setup supports only the batch mode of certain
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simulators. However, there should be no problems to integrate the testbench
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and RTL code into arbitrary simulation environments.
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The main file for compilation is Makefile.hier which contains all information
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regarding the dependencies of the source files and their compilation
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order. There is a dedicated file for each supported simulator that maps the
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generic information of Makefile.hier to object files specific to the given
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simulator.
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Compilation is based on the make-utility, thus invocation looks like this:
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$ make -f Makefile.
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where denotes one of the supported simulators:
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* Makefile.ghdl
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Tristan Gingold's GHDL simulator/compiler, a VHDL front-end for gcc.
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http://ghdl.free.fr/
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* Makefile.simili
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DISCONTINUED
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VHDL Simili, a VHDL simulator by Symphony EDA
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http://www.symphonyeda.com/
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Make will analyze all VHDL files (RTL and testbench code) and elaborate all
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three testbench top-levels if appropriate for the chosen simulator:
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* tb_behav_c0
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The main testbench for regression testing.
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Instantiates the plain t48_core and provides internal RAM (256 bytes) and
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ROM (2k bytes) plus 2k bytes of external ROM.
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* tb_t8048_behav_c0
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The testbench for the t8048 sample system.
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* tb_t8039_behav_c0
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The testbench for the 8039 sample system.
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* tb_t8243_behav_c0
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Testbench containing the t48_core and the synchronous t8243 flavour.
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* tb_t8048_t8243_behav_c0
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Testbench containing the t8048 and the asynchronous t8243 toplevel.
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Each Makefile has a 'clean' target to delete all intermediate data:
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$ make -f Makefile. clean
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The basic simple sequence list can be found in COMPILE_LIST. This can be
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useful to quickly set up the analyze stage of any compiler or
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synthesizer. Especially when synthesizing the code, you want to skip the VHDL
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configurations in *-c.vhd and everything below the bench/ directory.
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Preparation of the ROM Files
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----------------------------
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All testbenches listed above need two files in hex-format. They contain the
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program for the T48 core and are loaded into internal and external ROM at
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simulation startup. Their existance is mandatory as they are referenced in the
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VHDL code of the ROM model lpm_rom.vhd. In case they are missing, the
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simulation will stop immediately after elaborating the design.
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These files are:
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* rom_t49.hex
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Internal ROM contents for 8x49 derivatives,
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address range 000H to 7FFH.
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Intel hex format, starting at address 000H.
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* rom_t49_ext.hex
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External ROM contents for t8x49 derivatives,
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address range 800H to FFFH.
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Intel hex format, starting at address 800H.
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* rom_t48.hex
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Internal ROM contents for t8x48 derivatives,
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address range 000H to 3FFH.
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Intel hex format, starting at address 000H.
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* rom_t48_ext.hex
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External ROM contents for t8x48 derivatives,
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address range 400H to FFFH.
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Intel hex format, starting at address 000H.
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* rom_t3x.hex
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Internal ROM contents for t803x derivatives,
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empty.
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* rom_t3x_ext.hex
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External ROM contents for t803x derivatives,
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address range 000H to FFFH.
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Intel hex format, starting at address 000H.
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The verification flow for the T48 project generates these files
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automatically from the assembler source files.
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All regression tests and the general purpose software is organized in a cell
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structure. Currently, this means that the software for a cell is contained in
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a dedicated directory where the assembler run takes place. In the future,
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there will be more aspects to a cell.
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Assembling, linking and putting the hex-files in place is under the control of
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the make-mechanism. E.g. to assemble the source code of a cell, issue the
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following command:
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$ make -f $VERIF_DIR/include/Makefile.cell
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This generates the linker file (test.p) and distributes its contents to the
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required ROM files for internal and external program ROM. The target 'simu'
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copies these files automatically to the simulation directory. So most likely,
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for running a test case or any other software, you will want to issue:
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$ make -f VERIF_DIR/include/Makefile.cell all clean
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The 'all' target generates hex files for all supported testbenches.
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The only supported assembler is Alfred Arnold's macroassembler AS. See
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http://john.ccac.rwth-aachen.de:8000/as/
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Verification Environment
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------------------------
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The verification environment consists of a number of test programs. They are
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all self-checking. I.e. after testing the targeted functionality, they emit a
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pass/fail information. This information is detected by the testbench which
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stops the simulation and prints out the simulation result. This is the default
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mechanism for stopping the VHDL simulation.
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Pass/fail is signalled by a certain sequence of the accumulator contents:
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1) Accumulator contains AAH
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2) Accumulator contains 55H
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3) Accumulator contains 01H -> Pass
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Accumulator contains 00H -> Fail
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The detection is modelled like a state machine and in case the sequence is of
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bytes inside the accumulator does not match, the detection process restarts
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from the beginning. This mechanism is part of all verification tests.
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The complete regression suite can be executed with the run_regression.pl
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script. For each test cell, it steps through the sequence
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1) Assemble the source code
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2) Run the compiled VHDL design (currently only GHDL)
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3) Optionally perform a dump compare against the C-model
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It is highly recommended to redirect the output of run_regression.pl into a
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file. Otherwise, analyzing the messages related to each test cell is almost
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impossible.
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FPGA Implementation
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-------------------
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All of the design files contain pure RTL code. Also the RAM for the data
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memory is described by generic RTL code. It should be translated automatically
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by the tool chain to a technology specific RAM macro.
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There is a generic method for the program memory ROM as well, although this
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project uses a flow where hex-files are loaded by lpm_rom.vhd as the default
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method. Convert the ROM image to an RTL VHDL file with one of the two
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following commands (either from hex or bin format):
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$ hex2rom -b [rom image file] rom_t48 10l8s > rom_t48.vhd
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$ hex2rom -b [rom image file] rom_t49 11l8s > rom_t49.vhd
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The option -b specifies that [rom image file] contains binary data. Skip this
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option to process a file in hex format.
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These resulting RTL representations are instantiated by t48_rom-struct-a.vhd
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and t49_rom-struct-a.vhd. Altera and Xilinx design tools will detect and
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extract the ROM and turn it into a memory macro.
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