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arniml |
-------------------------------------------------------------------------------
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--
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-- The testbench for t8048 driving a t8243.
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--
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-- $Id: tb_t8048_t8243.vhd,v 1.1 2006-07-13 22:55:10 arniml Exp $
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--
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-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity tb_t8048_t8243 is
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end tb_t8048_t8243;
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use work.t48_core_comp_pack.generic_ram_ena;
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use work.t48_system_comp_pack.t8048;
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use work.t8243_comp_pack.t8243;
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use work.t48_tb_pack.all;
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architecture behav of tb_t8048_t8243 is
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-- clock period, 11 MHz
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constant period_c : time := 90 ns;
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component lpm_rom
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generic (
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LPM_WIDTH : positive;
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LPM_TYPE : string := "LPM_ROM";
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LPM_WIDTHAD : positive;
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LPM_NUMWORDS : natural := 0;
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LPM_FILE : string;
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LPM_ADDRESS_CONTROL : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_HINT : string := "UNUSED"
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);
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port (
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address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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inclock : in std_logic;
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outclock : in std_logic;
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memenab : in std_logic;
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q : out std_logic_vector(LPM_WIDTH-1 downto 0)
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);
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end component;
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signal xtal_s : std_logic;
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signal res_n_s : std_logic;
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signal int_n_s : std_logic;
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signal ale_s : std_logic;
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signal psen_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal p4_b : std_logic_vector( 3 downto 0);
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signal p5_b : std_logic_vector( 3 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal ext_mem_addr_s : std_logic_vector(11 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_we_s : std_logic;
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signal ext_rom_data_s : std_logic_vector( 7 downto 0);
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signal rd_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal zero_s : std_logic;
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signal one_s : std_logic;
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begin
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zero_s <= '0';
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one_s <= '1';
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p2_b <= (others => 'H');
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p1_b <= (others => 'H');
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-----------------------------------------------------------------------------
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-- External ROM, 3k bytes
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-- Initialized by file t48_ext_rom.hex.
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-----------------------------------------------------------------------------
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ext_rom_b : lpm_rom
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generic map (
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LPM_WIDTH => 8,
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LPM_TYPE => "LPM_ROM",
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LPM_WIDTHAD => 12,
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LPM_NUMWORDS => 3 * (2 ** 10),
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LPM_FILE => "rom_t48_ext.hex",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_HINT => "UNUSED"
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)
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port map (
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address => ext_mem_addr_s,
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inclock => xtal_s,
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outclock => zero_s, -- unused
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memenab => one_s,
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q => ext_rom_data_s
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);
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ext_ram_b : generic_ram_ena
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generic map (
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addr_width_g => 8,
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data_width_g => 8
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)
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port map (
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clk_i => xtal_s,
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a_i => ext_mem_addr_s(7 downto 0),
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we_i => ext_ram_we_s,
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ena_i => one_s,
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d_i => db_b,
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d_o => ext_ram_data_from_s
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);
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t8048_b : t8048
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port map (
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xtal_i => xtal_s,
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reset_n_i => res_n_s,
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t0_b => p1_b(0),
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int_n_i => int_n_s,
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ea_i => zero_s,
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rd_n_o => rd_n_s,
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psen_n_o => psen_n_s,
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wr_n_o => wr_n_s,
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ale_o => ale_s,
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db_b => db_b,
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t1_i => p1_b(1),
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p2_b => p2_b,
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p1_b => p1_b,
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prog_n_o => prog_n_s
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);
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t8243_b : t8243
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port map (
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cs_n_i => zero_s,
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prog_n_i => prog_n_s,
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p2_b => p2_b(3 downto 0),
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p4_b => p4_b,
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p5_b => p5_b,
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p6_b => p4_b,
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p7_b => p5_b
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);
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p4_b <= (others => 'H');
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p5_b <= (others => 'H');
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-----------------------------------------------------------------------------
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-- Read from external memory
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--
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db_b <= ext_rom_data_s
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when psen_n_s = '0' else
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(others => 'Z');
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db_b <= ext_ram_data_from_s
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when rd_n_s = '0' else
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(others => 'Z');
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External RAM access signals
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--
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ext_ram: process (wr_n_s,
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ale_s,
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p2_b,
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db_b)
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begin
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-- lowest 1k of external ROM is not used
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ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
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if ale_s'event and ale_s = '0' then
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if not is_X(db_b) then
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ext_mem_addr_s(7 downto 0) <= db_b;
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else
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ext_mem_addr_s(7 downto 0) <= (others => '0');
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end if;
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end if;
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if wr_n_s'event and wr_n_s = '1' then
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ext_ram_we_s <= '0';
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end if;
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if wr_n_s'event and wr_n_s = '0' then
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ext_ram_we_s <= '1';
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end if;
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end process ext_ram;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- The clock generator
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--
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clk_gen: process
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begin
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xtal_s <= '0';
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wait for period_c/2;
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xtal_s <= '1';
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wait for period_c/2;
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end process clk_gen;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- The reset generator
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--
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res_gen: process
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begin
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res_n_s <= '0';
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wait for 5 * period_c;
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res_n_s <= '1';
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wait;
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end process res_gen;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- The interrupt generator
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--
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int_gen: process
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begin
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int_n_s <= '1';
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wait for 750 * period_c;
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int_n_s <= '0';
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wait for 45 * period_c;
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end process int_gen;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- End of simulation detection
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--
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eos: process
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begin
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outer: loop
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wait on tb_accu_s;
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if tb_accu_s = "10101010" then
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wait on tb_accu_s;
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if tb_accu_s = "01010101" then
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wait on tb_accu_s;
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if tb_accu_s = "00000001" then
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-- wait for instruction strobe of this move
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wait until tb_istrobe_s'event and tb_istrobe_s = '1';
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-- wait for next strobe
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wait until tb_istrobe_s'event and tb_istrobe_s = '1';
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assert false
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report "Simulation Result: PASS."
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severity note;
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else
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assert false
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report "Simulation Result: FAIL."
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severity note;
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end if;
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assert false
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report "End of simulation reached."
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severity failure;
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end if;
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end if;
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end loop;
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end process eos;
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--
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-----------------------------------------------------------------------------
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end behav;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.7 2006/06/24 00:51:50 arniml
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-- comment added about lower 1k of external ROM
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--
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-- Revision 1.6 2006/06/22 00:21:28 arniml
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-- added external ROM
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--
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-- Revision 1.5 2006/06/21 01:04:05 arniml
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-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
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--
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-- Revision 1.4 2004/04/18 19:00:58 arniml
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-- connect T0 and T1 to P1
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--
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-- Revision 1.3 2004/04/14 20:57:44 arniml
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-- wait for instruction strobe after final end-of-simulation detection
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-- this ensures that the last mov instruction is part of the dump and
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-- enables 100% matching with i8039 simulator
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--
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-- Revision 1.2 2004/03/26 22:39:28 arniml
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-- enhance simulation result string
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--
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-- Revision 1.1 2004/03/24 21:42:10 arniml
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-- initial check-in
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--
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-------------------------------------------------------------------------------
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