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[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] [t8243/] [t8243_async_notri.vhd] - Blame information for rev 325

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1 247 arniml
-------------------------------------------------------------------------------
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--
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-- The T8243 asynchronous toplevel without tri-state signals
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--
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-- $Id: t8243_async_notri.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
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-- $Name: not supported by cvs2svn $
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--
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-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity t8243_async_notri is
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  port (
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    -- System Interface -------------------------------------------------------
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    reset_n_i : in  std_logic;
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    -- Control Interface ------------------------------------------------------
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    cs_n_i    : in  std_logic;
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    prog_n_i  : in  std_logic;
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    -- Port 2 Interface -------------------------------------------------------
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    p2_i      : in  std_logic_vector(3 downto 0);
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    p2_o      : out std_logic_vector(3 downto 0);
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    p2_en_o   : out std_logic;
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    -- Port 4 Interface -------------------------------------------------------
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    p4_i      : in  std_logic_vector(3 downto 0);
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    p4_o      : out std_logic_vector(3 downto 0);
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    p4_en_o   : out std_logic;
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    -- Port 5 Interface -------------------------------------------------------
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    p5_i      : in  std_logic_vector(3 downto 0);
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    p5_o      : out std_logic_vector(3 downto 0);
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    p5_en_o   : out std_logic;
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    -- Port 6 Interface -------------------------------------------------------
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    p6_i      : in  std_logic_vector(3 downto 0);
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    p6_o      : out std_logic_vector(3 downto 0);
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    p6_en_o   : out std_logic;
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    -- Port 7 Interface -------------------------------------------------------
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    p7_i      : in  std_logic_vector(3 downto 0);
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    p7_o      : out std_logic_vector(3 downto 0);
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    p7_en_o   : out std_logic
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  );
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end t8243_async_notri;
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use work.t8243_comp_pack.t8243_core;
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architecture struct of t8243_async_notri is
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  signal vdd_s : std_logic;
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begin
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  vdd_s <= '1';
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  -----------------------------------------------------------------------------
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  -- The T8243 Core
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  -----------------------------------------------------------------------------
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  t8243_core_b : t8243_core
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    generic map (
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      clk_fall_level_g => 0
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    )
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    port map (
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      clk_i         => prog_n_i,
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      clk_rise_en_i => vdd_s,
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      clk_fall_en_i => vdd_s,
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      reset_n_i     => reset_n_i,
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      cs_n_i        => cs_n_i,
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      prog_n_i      => prog_n_i,
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      p2_i          => p2_i,
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      p2_o          => p2_o,
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      p2_en_o       => p2_en_o,
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      p4_i          => p4_i,
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      p4_o          => p4_o,
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      p4_en_o       => p4_en_o,
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      p5_i          => p5_i,
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      p5_o          => p5_o,
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      p5_en_o       => p5_en_o,
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      p6_i          => p6_i,
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      p6_o          => p6_o,
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      p6_en_o       => p6_en_o,
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      p7_i          => p7_i,
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      p7_o          => p7_o,
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      p7_en_o       => p7_en_o
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    );
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end struct;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-------------------------------------------------------------------------------

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