OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [rtl/] [vhdl/] [t8243/] [t8243_comp_pack-p.vhd] - Blame information for rev 325

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 247 arniml 
-------------------------------------------------------------------------------
2 
--
3 
-- $Id: t8243_comp_pack-p.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
4 
--
5 
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
6 
--
7 
-- All rights reserved
8 
--
9 
-------------------------------------------------------------------------------
10 
 
11 
library ieee;
12 
use ieee.std_logic_1164.all;
13 
 
14 
package t8243_comp_pack is
15 
 
16 
  component t8243_core
17 
    generic (
18 
      clk_fall_level_g : integer := 0
19 
    );
20 
    port (
21 
      -- System Interface -----------------------------------------------------
22 
      clk_i         : in  std_logic;
23 
      clk_rise_en_i : in  std_logic;
24 
      clk_fall_en_i : in  std_logic;
25 
      reset_n_i     : in  std_logic;
26 
      -- Control Interface ----------------------------------------------------
27 
      cs_n_i        : in  std_logic;
28 
      prog_n_i      : in  std_logic;
29 
      -- Port 2 Interface -----------------------------------------------------
30 
      p2_i          : in  std_logic_vector(3 downto 0);
31 
      p2_o          : out std_logic_vector(3 downto 0);
32 
      p2_en_o       : out std_logic;
33 
      -- Port 4 Interface -----------------------------------------------------
34 
      p4_i          : in  std_logic_vector(3 downto 0);
35 
      p4_o          : out std_logic_vector(3 downto 0);
36 
      p4_en_o       : out std_logic;
37 
      -- Port 5 Interface -----------------------------------------------------
38 
      p5_i          : in  std_logic_vector(3 downto 0);
39 
      p5_o          : out std_logic_vector(3 downto 0);
40 
      p5_en_o       : out std_logic;
41 
      -- Port 6 Interface -----------------------------------------------------
42 
      p6_i          : in  std_logic_vector(3 downto 0);
43 
      p6_o          : out std_logic_vector(3 downto 0);
44 
      p6_en_o       : out std_logic;
45 
      -- Port 7 Interface -----------------------------------------------------
46 
      p7_i          : in  std_logic_vector(3 downto 0);
47 
      p7_o          : out std_logic_vector(3 downto 0);
48 
      p7_en_o       : out std_logic
49 
    );
50 
  end component;
51 
 
52 
  component t8243_sync_notri
53 
    port (
54 
      -- System Interface -----------------------------------------------------
55 
      clk_i     : in  std_logic;
56 
      clk_en_i  : in  std_logic;
57 
      reset_n_i : in  std_logic;
58 
      -- Control Interface ----------------------------------------------------
59 
      cs_n_i    : in  std_logic;
60 
      prog_n_i  : in  std_logic;
61 
      -- Port 2 Interface -----------------------------------------------------
62 
      p2_i      : in  std_logic_vector(3 downto 0);
63 
      p2_o      : out std_logic_vector(3 downto 0);
64 
      p2_en_o   : out std_logic;
65 
      -- Port 4 Interface -----------------------------------------------------
66 
      p4_i      : in  std_logic_vector(3 downto 0);
67 
      p4_o      : out std_logic_vector(3 downto 0);
68 
      p4_en_o   : out std_logic;
69 
      -- Port 5 Interface -----------------------------------------------------
70 
      p5_i      : in  std_logic_vector(3 downto 0);
71 
      p5_o      : out std_logic_vector(3 downto 0);
72 
      p5_en_o   : out std_logic;
73 
      -- Port 6 Interface -----------------------------------------------------
74 
      p6_i      : in  std_logic_vector(3 downto 0);
75 
      p6_o      : out std_logic_vector(3 downto 0);
76 
      p6_en_o   : out std_logic;
77 
      -- Port 7 Interface -----------------------------------------------------
78 
      p7_i      : in  std_logic_vector(3 downto 0);
79 
      p7_o      : out std_logic_vector(3 downto 0);
80 
      p7_en_o   : out std_logic
81 
    );
82 
  end component;
83 
 
84 
  component t8243_async_notri
85 
    port (
86 
      -- System Interface -----------------------------------------------------
87 
      reset_n_i : in  std_logic;
88 
      -- Control Interface ----------------------------------------------------
89 
      cs_n_i    : in  std_logic;
90 
      prog_n_i  : in  std_logic;
91 
      -- Port 2 Interface -----------------------------------------------------
92 
      p2_i      : in  std_logic_vector(3 downto 0);
93 
      p2_o      : out std_logic_vector(3 downto 0);
94 
      p2_en_o   : out std_logic;
95 
      -- Port 4 Interface -----------------------------------------------------
96 
      p4_i      : in  std_logic_vector(3 downto 0);
97 
      p4_o      : out std_logic_vector(3 downto 0);
98 
      p4_en_o   : out std_logic;
99 
      -- Port 5 Interface -----------------------------------------------------
100 
      p5_i      : in  std_logic_vector(3 downto 0);
101 
      p5_o      : out std_logic_vector(3 downto 0);
102 
      p5_en_o   : out std_logic;
103 
      -- Port 6 Interface -----------------------------------------------------
104 
      p6_i      : in  std_logic_vector(3 downto 0);
105 
      p6_o      : out std_logic_vector(3 downto 0);
106 
      p6_en_o   : out std_logic;
107 
      -- Port 7 Interface -----------------------------------------------------
108 
      p7_i      : in  std_logic_vector(3 downto 0);
109 
      p7_o      : out std_logic_vector(3 downto 0);
110 
      p7_en_o   : out std_logic
111 
    );
112 
  end component;
113 
 
114 
  component t8243
115 
    port (
116 
      -- Control Interface ----------------------------------------------------
117 
      cs_n_i   : in    std_logic;
118 
      prog_n_i : in    std_logic;
119 
      -- Port 2 Interface -----------------------------------------------------
120 
      p2_b     : inout std_logic_vector(3 downto 0);
121 
      -- Port 4 Interface -----------------------------------------------------
122 
      p4_b     : inout std_logic_vector(3 downto 0);
123 
      -- Port 5 Interface -----------------------------------------------------
124 
      p5_b     : inout std_logic_vector(3 downto 0);
125 
      -- Port 6 Interface -----------------------------------------------------
126 
      p6_b     : inout std_logic_vector(3 downto 0);
127 
      -- Port 7 Interface -----------------------------------------------------
128 
      p7_b     : inout std_logic_vector(3 downto 0)
129 
    );
130 
  end component;
131 
 
132 
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.