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[/] [t48/] [tags/] [rel_1_1/] [sw/] [verif/] [black_box/] [rb/] [misc/] [test.asm] - Blame information for rev 12

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1 12 arniml 
        ;; *******************************************************************
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        ;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
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        ;;
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        ;; Test several operations in conjunction with RB-switching.
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        ;; *******************************************************************
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        INCLUDE "cpu.inc"
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        INCLUDE "pass_fail.inc"
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        ORG     0
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        ;; Start of test
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        ;; fill data memory with 0
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        clr     a
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        mov     r0, a
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fill_loop:
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        mov     @r0, a
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        djnz    r0, fill_loop
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        ;; set up both register banks with indirect writes
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        mov     r0, #01FH
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        mov     r1, #008H
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fill_rb1_loop:
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        mov     a, r0
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        mov     @r0, a
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        dec     r0
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        djnz    r1, fill_rb1_loop
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        mov     r0, #007H
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fill_rb0_loop:
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        mov     a, r0
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        mov     @r0, a
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        djnz    r0, fill_rb0_loop
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        mov     a, r0
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        mov     @r0, a
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        ;; check RB0
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        call    check_rb0
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        ;; check RB1
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        sel     rb1
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        call    check_rb1
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        ;; check RB0 again
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        sel     rb0
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        call    check_rb0
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        ;; check memory between RB0 and RB1 for 0
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        mov     r0, #00EH       ; check 14 bytes
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        mov     r1, #00AH       ; starting from address A
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chk_loop1:
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        mov     a, @r1
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        jnz     fail
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        inc     r1
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        djnz    r0, chk_loop1
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        ;; check memory above RB1 for 0
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        mov     r0, #0100H - 0020H ; check 256-32 bytes
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        mov     r1, #020H       ; starting from address 20H
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chk_loop2:
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        mov     a, @r1
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        jnz     fail
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        inc     r1
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        djnz    r0, chk_loop2
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        ;; now use RB1 to indirect address register 0-7
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        mov     r1, #001H       ; restore r1
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        mov     r0, #000H       ; restore r0, set trap
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        sel     rb1
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        mov     r0, #007H
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ind_chk_loop:
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        mov     a, @r0
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        cpl     a
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        add     a, r0
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        cpl     a
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        jnz     fail
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        djnz    r0, ind_chk_loop
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pass:   PASS
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fail:   FAIL
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        ORG     0300H
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check_rb0:
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        mov     a, r0
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        jnz     fail_p3
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        mov     a,r1
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        add     a, #0FFH
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        jnz     fail_p3
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        mov     a,r2
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        add     a, #0FEH
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        jnz     fail_p3
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        mov     a,r3
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        add     a, #0FDH
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        jnz     fail_p3
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        mov     a,r4
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        add     a, #0FCH
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        jnz     fail_p3
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        mov     a,r5
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        add     a, #0FBH
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        jnz     fail_p3
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        mov     a,r6
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        add     a, #0FAH
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        jnz     fail_p3
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        mov     a,r7
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        add     a, #0F9H
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        jnz     fail_p3
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        ret
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check_rb1:
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        mov     a, r0
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        add     a, #0E8H
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        jnz     fail_p3
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        mov     a,r1
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        add     a, #0E7H
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        jnz     fail_p3
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        mov     a,r2
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        add     a, #0E6H
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        jnz     fail_p3
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        mov     a,r3
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        add     a, #0E5H
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        jnz     fail_p3
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        mov     a,r4
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        add     a, #0E4H
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        jnz     fail_p3
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        mov     a,r5
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        add     a, #0E3H
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        jnz     fail_p3
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        mov     a,r6
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        add     a, #0E2H
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        jnz     fail_p3
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        mov     a,r7
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        add     a, #0E1H
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        jnz     fail_p3
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        ret
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fail_p3:
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        FAIL

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