Subversion Repositories t48

Change log for the T48 uController core

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Version: $Id: CHANGELOG 328 2022-12-30 17:57:47Z arniml $

Release 1.3

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Added support for UPI-41/41A/41AH/42/42AH device family.

Release 1.2

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Maintenance release for SVN updates.

Release 1.1

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* code optimizations in the decoder to reduce LUT usage with

  Xilinx ISE/XST.

* fix tb_t8048 and tb_t8049 with respect to P1[0]->T0 signalling.

* synthesis templates for QuartusII and ISE.

* added dedicated version of hex2rom utility for RTL ROM generation

  (keeps compatibility with QuartusII 7.2).

* better describe RTL ROM and RAM macros.

Release 1.0

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* T8243 I/O expander added to project

* Bugfix for "Deassertion of PROG too early"

  PROG is deasserted at end of XTAL3 now.

  Applied in clock_ctrl.vhd 1.12

* new input xtal_en_i gates xtal_i base clock

* counter_q in timer module has asynchronous reset

* replaced syn_rom and syn_ram with t48_rom and generic_ram_ena

* verification environment updated for new testbenches

Release 0.6.1 BETA

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* Bugfix for "PROBLEM WHEN INT AND JMP"

  Suppress assertion of bus_read_bus_s when interrupt is pending.

  Applied in decoder.vhd 1.21

* Bugfix for "P2 Port value restored after expander access"

  Applied in p2.vhd 1.8

* change low impedance markers for P2

  separate marker for low and high part

* shift assertion of ALE and PROG to xtal3

* properly drive P1 and P2 with low impedance markers

* suppress p2_output_pch_o when MOVX operation is accessing the

  external memory

* suppress p2_output_pch_o when p2_output_exp is active

* operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3

Release 0.6 BETA

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* Bugfix for "Wrong clock applied to T0"

  Applied in clock_ctrl.vhd 1.7

             t48_core.vhd 1.8

* Introduced "notri" hierarchy for t8048 and t8039 system.

  This allows the usage of such a system without tri-state signals.

* Fixed lpm_memory type definition in lpm_rom.vhd and lpm_ram.vhd.

* New Wishbone master module: wb_master.vhd

* New system toplevel: t8050_wb.vhd

  Contains the Wishbone master.

* Prefixed all design units with 't48_'.

* Updates for running the core with full xtal clock. Should work now.

* Move latching of BUS to MSTATE2 in decoder.vhd

    -> sample BUS at the end of RD'

* Fix a glitch on PCH when an interrupt occurs during external

  program memory fetch in decoder.vhd

* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted

              by interrupt"

  and        "Return address of CALL to Program Memory Bank 1 corrupted

              by interrupt"

  Applied in int.vhd 1.5

* Bugfix for "MSB of Program Counter changed upon PC increment"

  Applied in pmem_ctrl.vhd 1.4

* Preliminary Integration Manual added.

Release 0.5 BETA

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* Bugfix for "P1 constantly in push-pull mode in t8048"

  Applied in t8048.vhd 1.3

* Bugfix for "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"

  Applied in decoder.vhd 1.16

             db_bus.vhd 1.3

  Updated testcase black_box/ins.

* P1, P2 and BUS are written during the first instruction cycle of the

  OUTL instruction. This matches the descirption in the User Manual.

  The previous implementation updated these ports at the end of the

  second instruction cycle.

  Applied in decoder.vhd 1.16

* Shifted deassertion of RD and WR to end of XTAL3 of machine state 2.

  The previous deassertion at the end of XTAL2 was not according to the

  User Manual. Their rising edge can now be used as a read/write strobe.

  On the other hand, PROG is still deasserted at the end of XTAL3. This

  is needed to for the rising edge of PROG within valid P2 expander data.

  Applied in clock_ctrl.vhd 1.6