Subversion Repositories t51

--

-- File I/O test-bench utilities

--

-- Version : 0146

--

-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)

--

-- All rights reserved

--

-- Redistribution and use in source and synthezised forms, with or without

-- modification, are permitted provided that the following conditions are met:

--

-- Redistributions of source code must retain the above copyright notice,

-- this list of conditions and the following disclaimer.

--

-- Redistributions in synthesized form must reproduce the above copyright

-- notice, this list of conditions and the following disclaimer in the

-- documentation and/or other materials provided with the distribution.

--

-- Neither the name of the author nor the names of other contributors may

-- be used to endorse or promote products derived from this software without

-- specific prior written permission.

--

-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,

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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE

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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

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--

-- Please report bugs to the author, but before you do so, please

-- make sure that this is not a derivative work and that

-- you have the latest version of this file.

--

-- The latest version of this file can be found at:

--      http://www.opencores.org/cvsweb.shtml/t51/

--

-- Limitations :

--

-- File history :

--

library IEEE;

use IEEE.std_logic_1164.all;

use std.textio.all;

entity IntegerLog is

        generic(

                FileName                : string

        );

        port(

                Clk                             : in std_logic;

                En                              : in std_logic;

                Data                    : in integer

        );

end IntegerLog;

architecture behaviour of IntegerLog is

begin

        process (Clk)

                file OutFile : text open write_mode is FileName;

                variable l : line;

        begin

                if Clk'event and Clk = '1' and En = '1' and now > 0 ns then

                        write(l, Data);

                        writeline(OutFile, l);

                end if;

        end process;

end;