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[/] [t65/] [trunk/] [rtl/] [vhdl/] [DebugSystemXR.vhd] - Blame information for rev 13

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-- 6502, Monitor ROM, external SRAM interface and two 16450 UARTs
-- that can be synthesized and used with
-- the NoICE debugger that can be found at
-- http://www.noicedebugger.com/
 
library IEEE;
use IEEE.std_logic_1164.all;
 
entity DebugSystemXR is
        port(
                Reset_n         : in std_logic;
                Clk                     : in std_logic;
                NMI_n           : in std_logic;
                OE_n            : out std_logic;
                WE_n            : out std_logic;
                RAMCS_n         : out std_logic;
                ROMCS_n         : out std_logic;
                PGM_n           : out std_logic;
                A                       : out std_logic_vector(16 downto 0);
                D                       : inout std_logic_vector(7 downto 0);
                RXD0            : in std_logic;
                CTS0            : in std_logic;
                DSR0            : in std_logic;
                RI0                     : in std_logic;
                DCD0            : in std_logic;
                RXD1            : in std_logic;
                CTS1            : in std_logic;
                DSR1            : in std_logic;
                RI1                     : in std_logic;
                DCD1            : in std_logic;
                TXD0            : out std_logic;
                RTS0            : out std_logic;
                DTR0            : out std_logic;
                TXD1            : out std_logic;
                RTS1            : out std_logic;
                DTR1            : out std_logic
        );
end entity DebugSystemXR;
 
architecture struct of DebugSystemXR is
 
        signal Res_n_s          : std_logic;
        signal Rd_n                     : std_logic;
        signal Wr_n                     : std_logic;
        signal R_W_n            : std_logic;
        signal A_i                      : std_logic_vector(23 downto 0);
        signal D_i                      : std_logic_vector(7 downto 0);
        signal ROM_D            : std_logic_vector(7 downto 0);
        signal UART0_D          : std_logic_vector(7 downto 0);
        signal UART1_D          : std_logic_vector(7 downto 0);
        signal CPU_D            : std_logic_vector(7 downto 0);
 
        signal Rdy                      : std_logic;
 
        signal IOWR_n           : std_logic;
        signal RAMCS_n_i        : std_logic;
        signal UART0CS_n        : std_logic;
        signal UART1CS_n        : std_logic;
 
        signal BaudOut0         : std_logic;
        signal BaudOut1         : std_logic;
 
begin
 
        Rd_n <= not R_W_n or not Rdy;
        Wr_n <= R_W_n or not Rdy;
        OE_n <= not R_W_n;
        WE_n <= Wr_n;
        RAMCS_n <= RAMCS_n_i;
        ROMCS_n <= '1';
        PGM_n <= '1';
        A(14 downto 0) <= A_i(14 downto 0);
        A(16 downto 15) <= "00";
        D <= D_i when R_W_n = '0' else "ZZZZZZZZ";
 
        process (Reset_n, Clk)
        begin
                if Reset_n = '0' then
                        Res_n_s <= '0';
                        Rdy <= '0';
                elsif Clk'event and Clk = '1' then
                        Res_n_s <= '1';
                        Rdy <= not Rdy;
                end if;
        end process;
 
        RAMCS_n_i <= A_i(15);
        UART0CS_n <= '0' when A_i(15 downto 3) = "1000000000000" else '1';
        UART1CS_n <= '0' when A_i(15 downto 3) = "1000000010000" else '1';
 
        CPU_D <=
                D when RAMCS_n_i = '0' else
                UART0_D when UART0CS_n = '0' else
                UART1_D when UART1CS_n = '0' else
                ROM_D;
 
        u0 : entity work.T65
                port map(
                        Mode => "00",
                        Res_n => Res_n_s,
                        Clk => Clk,
                        Rdy => Rdy,
                        Abort_n => '1',
                        IRQ_n => '1',
                        NMI_n => NMI_n,
                        SO_n => '1',
                        R_W_n => R_W_n,
                        Sync => open,
                        EF => open,
                        MF => open,
                        XF => open,
                        ML_n => open,
                        VP_n => open,
                        VDA => open,
                        VPA => open,
                        A => A_i,
                        DI => CPU_D,
                        DO => D_i);
 
        u1 : entity work.Mon65XR
                port map(
                        Clk => Clk,
                        A => A_i(9 downto 0),
                        D => ROM_D);
 
        u3 : entity work.T16450
                port map(
                        MR_n => Res_n_s,
                        XIn => Clk,
                        RClk => BaudOut0,
                        CS_n => UART0CS_n,
                        Rd_n => Rd_n,
                        Wr_n => Wr_n,
                        A => A_i(2 downto 0),
                        D_In => D_i,
                        D_Out => UART0_D,
                        SIn => RXD0,
                        CTS_n => CTS0,
                        DSR_n => DSR0,
                        RI_n => RI0,
                        DCD_n => DCD0,
                        SOut => TXD0,
                        RTS_n => RTS0,
                        DTR_n => DTR0,
                        OUT1_n => open,
                        OUT2_n => open,
                        BaudOut => BaudOut0,
                        Intr => open);
 
        u4 : entity work.T16450
                port map(
                        MR_n => Res_n_s,
                        XIn => Clk,
                        RClk => BaudOut1,
                        CS_n => UART1CS_n,
                        Rd_n => Rd_n,
                        Wr_n => Wr_n,
                        A => A_i(2 downto 0),
                        D_In => D_i,
                        D_Out => UART1_D,
                        SIn => RXD1,
                        CTS_n => CTS1,
                        DSR_n => DSR1,
                        RI_n => RI1,
                        DCD_n => DCD1,
                        SOut => TXD1,
                        RTS_n => RTS1,
                        DTR_n => DTR1,
                        OUT1_n => open,
                        OUT2_n => open,
                        BaudOut => BaudOut1,
                        Intr => open);
 
end;

Line No.	Rev	Author	Line
1	7	jesus	`-- 6502, Monitor ROM, external SRAM interface and two 16450 UARTs`
2			`-- that can be synthesized and used with`
3			`-- the NoICE debugger that can be found at`
4			`-- http://www.noicedebugger.com/`
5
6			`library IEEE;`
7			`use IEEE.std_logic_1164.all;`
8
9			`entity DebugSystemXR is`
10			`port(`
11			`Reset_n : in std_logic;`
12			`Clk : in std_logic;`
13			`NMI_n : in std_logic;`
14			`OE_n : out std_logic;`
15			`WE_n : out std_logic;`
16			`RAMCS_n : out std_logic;`
17			`ROMCS_n : out std_logic;`
18			`PGM_n : out std_logic;`
19			`A : out std_logic_vector(16 downto 0);`
20			`D : inout std_logic_vector(7 downto 0);`
21			`RXD0 : in std_logic;`
22			`CTS0 : in std_logic;`
23			`DSR0 : in std_logic;`
24			`RI0 : in std_logic;`
25			`DCD0 : in std_logic;`
26			`RXD1 : in std_logic;`
27			`CTS1 : in std_logic;`
28			`DSR1 : in std_logic;`
29			`RI1 : in std_logic;`
30			`DCD1 : in std_logic;`
31			`TXD0 : out std_logic;`
32			`RTS0 : out std_logic;`
33			`DTR0 : out std_logic;`
34			`TXD1 : out std_logic;`
35			`RTS1 : out std_logic;`
36			`DTR1 : out std_logic`
37			`);`
38			`end entity DebugSystemXR;`
39
40			`architecture struct of DebugSystemXR is`
41
42			`signal Res_n_s : std_logic;`
43			`signal Rd_n : std_logic;`
44			`signal Wr_n : std_logic;`
45			`signal R_W_n : std_logic;`
46			`signal A_i : std_logic_vector(23 downto 0);`
47			`signal D_i : std_logic_vector(7 downto 0);`
48			`signal ROM_D : std_logic_vector(7 downto 0);`
49			`signal UART0_D : std_logic_vector(7 downto 0);`
50			`signal UART1_D : std_logic_vector(7 downto 0);`
51			`signal CPU_D : std_logic_vector(7 downto 0);`
52
53			`signal Rdy : std_logic;`
54
55			`signal IOWR_n : std_logic;`
56			`signal RAMCS_n_i : std_logic;`
57			`signal UART0CS_n : std_logic;`
58			`signal UART1CS_n : std_logic;`
59
60			`signal BaudOut0 : std_logic;`
61			`signal BaudOut1 : std_logic;`
62
63			`begin`
64
65			`Rd_n <= not R_W_n or not Rdy;`
66			`Wr_n <= R_W_n or not Rdy;`
67			`OE_n <= not R_W_n;`
68			`WE_n <= Wr_n;`
69			`RAMCS_n <= RAMCS_n_i;`
70			`ROMCS_n <= '1';`
71			`PGM_n <= '1';`
72			`A(14 downto 0) <= A_i(14 downto 0);`
73			`A(16 downto 15) <= "00";`
74			`D <= D_i when R_W_n = '0' else "ZZZZZZZZ";`
75
76			`process (Reset_n, Clk)`
77			`begin`
78			`if Reset_n = '0' then`
79			`Res_n_s <= '0';`
80			`Rdy <= '0';`
81			`elsif Clk'event and Clk = '1' then`
82			`Res_n_s <= '1';`
83			`Rdy <= not Rdy;`
84			`end if;`
85			`end process;`
86
87			`RAMCS_n_i <= A_i(15);`
88			`UART0CS_n <= '0' when A_i(15 downto 3) = "1000000000000" else '1';`
89			`UART1CS_n <= '0' when A_i(15 downto 3) = "1000000010000" else '1';`
90
91			`CPU_D <=`
92			`D when RAMCS_n_i = '0' else`
93			`UART0_D when UART0CS_n = '0' else`
94			`UART1_D when UART1CS_n = '0' else`
95			`ROM_D;`
96
97			`u0 : entity work.T65`
98			`port map(`
99			`Mode => "00",`
100			`Res_n => Res_n_s,`
101			`Clk => Clk,`
102			`Rdy => Rdy,`
103			`Abort_n => '1',`
104			`IRQ_n => '1',`
105			`NMI_n => NMI_n,`
106			`SO_n => '1',`
107			`R_W_n => R_W_n,`
108			`Sync => open,`
109			`EF => open,`
110			`MF => open,`
111			`XF => open,`
112			`ML_n => open,`
113			`VP_n => open,`
114			`VDA => open,`
115			`VPA => open,`
116			`A => A_i,`
117			`DI => CPU_D,`
118			`DO => D_i);`
119
120			`u1 : entity work.Mon65XR`
121			`port map(`
122			`Clk => Clk,`
123			`A => A_i(9 downto 0),`
124			`D => ROM_D);`
125
126			`u3 : entity work.T16450`
127			`port map(`
128			`MR_n => Res_n_s,`
129			`XIn => Clk,`
130			`RClk => BaudOut0,`
131			`CS_n => UART0CS_n,`
132			`Rd_n => Rd_n,`
133			`Wr_n => Wr_n,`
134			`A => A_i(2 downto 0),`
135			`D_In => D_i,`
136			`D_Out => UART0_D,`
137			`SIn => RXD0,`
138			`CTS_n => CTS0,`
139			`DSR_n => DSR0,`
140			`RI_n => RI0,`
141			`DCD_n => DCD0,`
142			`SOut => TXD0,`
143			`RTS_n => RTS0,`
144			`DTR_n => DTR0,`
145			`OUT1_n => open,`
146			`OUT2_n => open,`
147			`BaudOut => BaudOut0,`
148			`Intr => open);`
149
150			`u4 : entity work.T16450`
151			`port map(`
152			`MR_n => Res_n_s,`
153			`XIn => Clk,`
154			`RClk => BaudOut1,`
155			`CS_n => UART1CS_n,`
156			`Rd_n => Rd_n,`
157			`Wr_n => Wr_n,`
158			`A => A_i(2 downto 0),`
159			`D_In => D_i,`
160			`D_Out => UART1_D,`
161			`SIn => RXD1,`
162			`CTS_n => CTS1,`
163			`DSR_n => DSR1,`
164			`RI_n => RI1,`
165			`DCD_n => DCD1,`
166			`SOut => TXD1,`
167			`RTS_n => RTS1,`
168			`DTR_n => DTR1,`
169			`OUT1_n => open,`
170			`OUT2_n => open,`
171			`BaudOut => BaudOut1,`
172			`Intr => open);`
173
174			`end;`

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[/] [t65/] [trunk/] [rtl/] [vhdl/] [DebugSystemXR.vhd] - Blame information for rev 13