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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Blame information for rev 155

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alu_chk.e
<'
import alu_components;
 
unit alu_chk_u {
        reg_a : byte;
        reg_x : byte;
        reg_y : byte;
        reg_status : byte;
        reg_result : byte;
 
        inst : alu_input_s;
        next_inst : alu_input_s;
 
        count_cycles : int;
        first_cycle : bool;
 
        keep first_cycle == TRUE;
        keep count_cycles == 0;
 
        store(input : alu_input_s) is {
                count_cycles = count_cycles + 1;
 
                //out ("CYCLE ", count_cycles, " STORE:");
                //print input;
 
                if (first_cycle) {
                        inst = input;
                        next_inst = input;
                }
                else {
                        inst = next_inst;
                        next_inst = input;
                };
 
        };
 
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
                if (first_cycle) {
                        first_cycle = FALSE;
                        reg_x = 0;
                        reg_y = 0;
                        reg_status = 8'b00100010;
                        reg_a = 0; // TODO: check this
                        reg_result = 0;
                }
                else {
                        //out ("CYCLE ", count_cycles, " COMPARE:");
                        //print inst;
 
                        case inst.input_kind {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute();
                                };
                                DISABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": just comparing");
                                };
                                RESET: {
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_a = 0; // TODO: check this
                                        reg_result = 0;
 
                                        return;
                                };
                                default: {
                                        dut_error("error at e code");
                                };
                        };
 
                        // here i have already calculated. must compare!
 
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
                                out("#########################################################");
                                print me;
                                print me.inst;
                                out("#########################################################");
                                print alu_result;
                                print alu_status;
                                print alu_x;
                                print alu_y;
 
                                dut_error("WRONG!");
                        };
                };
        };
 
        execute() is {
                case inst.alu_opcode {
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                        ADC_ZPG: { exec_sum(); };
                        ADC_ZPX: { exec_sum(); };
                        ADC_ABS: { exec_sum(); };
                        ADC_ABX: { exec_sum(); };
                        ADC_ABY: { exec_sum(); };
                        ADC_IDX: { exec_sum(); };
                        ADC_IDY: { exec_sum(); };
 
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
                        AND_ZPG: { exec_and(); };
                        AND_ZPX: { exec_and(); };
                        AND_ABS: { exec_and(); };
                        AND_ABX: { exec_and(); };
                        AND_ABY: { exec_and(); };
                        AND_IDX: { exec_and(); };
                        AND_IDY: { exec_and(); };
 
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
 
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
                        ASL_ZPX: { exec_asl_mem(); };
                        ASL_ABS: { exec_asl_mem(); };
                        ASL_ABX: { exec_asl_mem(); };
 
                        BCC_REL: {}; // nothing is done. these are all branches.
                        BCS_REL: {};
                        BEQ_REL: {};
                        BMI_REL: {};
                        BNE_REL: {};
                        BPL_REL: {};
                        BVC_REL: {};
                        BVS_REL: {};
 
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
                        BIT_ABS: { exec_bit(); };
 
                        BRK_IMP: { reg_status[4:4] = 1; };
 
                        CLC_IMP: { reg_status[0:0] = 0; };
                        CLD_IMP: { reg_status[3:3] = 0; };
                        CLI_IMP: { reg_status[2:2] = 0; };
                        CLV_IMP: { reg_status[6:6] = 0; };
 
                        default: {
                                out(inst.alu_opcode);
                                dut_error("unknown opcode");
                        }
                };
        };
 
        exec_bit() is {
                update_z(reg_a & inst.alu_a);
                reg_status[7:7] = inst.alu_a[7:7];
                reg_status[6:6] = inst.alu_a[6:6];
        };
 
        exec_asl_acc() is {
                reg_status[0:0] = reg_a[7:7];
                reg_a = reg_a * 2;
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_asl_mem() is {
                reg_status[0:0] = inst.alu_a[7:7];
                reg_result = inst.alu_a * 2;
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_and() is {
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_sum() is {
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
                reg_result = reg_a + inst.alu_a + reg_status[0:0];
                update_c(reg_a, inst.alu_a, reg_status[0:0]);
                update_v(reg_a, inst.alu_a, reg_result);
                update_z(reg_result);
                update_n(reg_result);
                reg_a = reg_result;
                //print me;
                //dut_error();
        };
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
                if (arg1 + arg2 + arg3 > 255) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                }
        };
 
        update_v(op1 : byte, op2 : byte, res : byte) is {
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
                        reg_status[6:6] = 1;
                }
                else {
                        reg_status[6:6] = 0;
                };
        };
 
        update_z(arg : byte) is {
                if (arg == 0) {
                        reg_status[1:1] = 1;
                }
                else {
                        reg_status[1:1] = 0;
                }
        };
 
 
        update_n(arg : byte) is {
                if (arg[7:7] == 1) {
                        reg_status[7:7] = 1;
                }
                else {
                        reg_status[7:7] = 0;
                }
        };
};
'>

Line No.	Rev	Author	Line
1	131	creep	`alu_chk.e`
2			`<'`
3			`import alu_components;`
4
5			`unit alu_chk_u {`
6			`reg_a : byte;`
7			`reg_x : byte;`
8			`reg_y : byte;`
9			`reg_status : byte;`
10	135	creep	`reg_result : byte;`
11	131	creep
12	132	creep	`inst : alu_input_s;`
13			`next_inst : alu_input_s;`
14
15	131	creep	`count_cycles : int;`
16			`first_cycle : bool;`
17
18			`keep first_cycle == TRUE;`
19			`keep count_cycles == 0;`
20
21			`store(input : alu_input_s) is {`
22	134	creep	`count_cycles = count_cycles + 1;`
23
24	153	creep	`//out ("CYCLE ", count_cycles, " STORE:");`
25			`//print input;`
26	132	creep
27			`if (first_cycle) {`
28			`inst = input;`
29			`next_inst = input;`
30			`}`
31			`else {`
32			`inst = next_inst;`
33			`next_inst = input;`
34			`};`
35
36	131	creep	`};`
37
38			`compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {`
39			`if (first_cycle) {`
40			`first_cycle = FALSE;`
41	143	creep	`reg_x = 0;`
42			`reg_y = 0;`
43			`reg_status = 8'b00100010;`
44	132	creep	`reg_a = 0; // TODO: check this`
45	135	creep	`reg_result = 0;`
46	131	creep	`}`
47	132	creep	`else {`
48	153	creep	`//out ("CYCLE ", count_cycles, " COMPARE:");`
49			`//print inst;`
50	134	creep
51	132	creep	`case inst.input_kind {`
52			`ENABLED_VALID: {`
53	153	creep	`//out("CYCLE ", count_cycles, ": executing and comparing");`
54	132	creep	`execute();`
55			`};`
56			`DISABLED_VALID: {`
57	153	creep	`//out("CYCLE ", count_cycles, ": just comparing");`
58	132	creep	`};`
59	143	creep	`RESET: {`
60	146	creep	`reg_x = 0;`
61			`reg_y = 0;`
62			`reg_status = 8'b00100010;`
63			`reg_a = 0; // TODO: check this`
64			`reg_result = 0;`
65
66	143	creep	`return;`
67			`};`
68	132	creep	`default: {`
69			`dut_error("error at e code");`
70			`};`
71			`};`
72
73	133	creep	`// here i have already calculated. must compare!`
74	143	creep
75	146	creep	`if ((reg_result != alu_result) \|\| (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {`
76	153	creep	`out("#########################################################");`
77	135	creep	`print me;`
78	155	creep	`print me.inst;`
79	153	creep	`out("#########################################################");`
80	134	creep	`print alu_result;`
81	135	creep	`print alu_status;`
82			`print alu_x;`
83			`print alu_y;`
84
85	133	creep	`dut_error("WRONG!");`
86			`};`
87	146	creep	`};`
88	131	creep	`};`
89	132	creep
90			`execute() is {`
91			`case inst.alu_opcode {`
92			`ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C`
93			`ADC_ZPG: { exec_sum(); };`
94			`ADC_ZPX: { exec_sum(); };`
95			`ADC_ABS: { exec_sum(); };`
96			`ADC_ABX: { exec_sum(); };`
97			`ADC_ABY: { exec_sum(); };`
98			`ADC_IDX: { exec_sum(); };`
99			`ADC_IDY: { exec_sum(); };`
100
101	133	creep	`AND_IMM: { exec_and(); }; // A,Z,N = A&M`
102	132	creep	`AND_ZPG: { exec_and(); };`
103			`AND_ZPX: { exec_and(); };`
104			`AND_ABS: { exec_and(); };`
105			`AND_ABX: { exec_and(); };`
106			`AND_ABY: { exec_and(); };`
107			`AND_IDX: { exec_and(); };`
108			`AND_IDY: { exec_and(); };`
109
110	135	creep	`ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2`
111	132	creep
112	135	creep	`ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2`
113			`ASL_ZPX: { exec_asl_mem(); };`
114			`ASL_ABS: { exec_asl_mem(); };`
115			`ASL_ABX: { exec_asl_mem(); };`
116
117	155	creep	`BCC_REL: {}; // nothing is done. these are all branches.`
118	153	creep	`BCS_REL: {};`
119			`BEQ_REL: {};`
120	155	creep	`BMI_REL: {};`
121			`BNE_REL: {};`
122			`BPL_REL: {};`
123			`BVC_REL: {};`
124			`BVS_REL: {};`
125	153	creep
126	155	creep	`BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6`
127			`BIT_ABS: { exec_bit(); };`
128
129			`BRK_IMP: { reg_status[4:4] = 1; };`
130
131			`CLC_IMP: { reg_status[0:0] = 0; };`
132			`CLD_IMP: { reg_status[3:3] = 0; };`
133			`CLI_IMP: { reg_status[2:2] = 0; };`
134			`CLV_IMP: { reg_status[6:6] = 0; };`
135
136	132	creep	`default: {`
137	155	creep	`out(inst.alu_opcode);`
138			`dut_error("unknown opcode");`
139	132	creep	`}`
140			`};`
141			`};`
142
143	155	creep	`exec_bit() is {`
144			`update_z(reg_a & inst.alu_a);`
145			`reg_status[7:7] = inst.alu_a[7:7];`
146			`reg_status[6:6] = inst.alu_a[6:6];`
147			`};`
148
149	135	creep	`exec_asl_acc() is {`
150			`reg_status[0:0] = reg_a[7:7];`
151			`reg_a = reg_a * 2;`
152			`update_z(reg_a);`
153			`update_n(reg_a);`
154			`reg_result = reg_a;`
155			`};`
156
157			`exec_asl_mem() is {`
158			`reg_status[0:0] = inst.alu_a[7:7];`
159			`reg_result = inst.alu_a * 2;`
160			`update_z(reg_result);`
161			`update_n(reg_result);`
162			`};`
163
164	132	creep	`exec_and() is {`
165	133	creep	`reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong`
166			`update_z(reg_a);`
167			`update_n(reg_a);`
168	135	creep	`reg_result = reg_a;`
169	132	creep	`};`
170
171			`exec_sum() is {`
172	153	creep	`//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);`
173	144	creep	`reg_result = reg_a + inst.alu_a + reg_status[0:0];`
174	143	creep	`update_c(reg_a, inst.alu_a, reg_status[0:0]);`
175	146	creep	`update_v(reg_a, inst.alu_a, reg_result);`
176	144	creep	`update_z(reg_result);`
177			`update_n(reg_result);`
178			`reg_a = reg_result;`
179	135	creep	`//print me;`
180	134	creep	`//dut_error();`
181	132	creep	`};`
182
183	143	creep	`update_c(arg1 : byte, arg2 : byte, arg3: bit) is {`
184	153	creep	`if (arg1 + arg2 + arg3 > 255) {`
185	132	creep	`reg_status[0:0] = 1;`
186			`}`
187			`else {`
188			`reg_status[0:0] = 0;`
189			`}`
190			`};`
191
192	146	creep	`update_v(op1 : byte, op2 : byte, res : byte) is {`
193			`if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {`
194			`reg_status[6:6] = 1;`
195			`}`
196			`else {`
197			`reg_status[6:6] = 0;`
198			`};`
199			`};`
200
201			`update_z(arg : byte) is {`
202			`if (arg == 0) {`
203			`reg_status[1:1] = 1;`
204			`}`
205			`else {`
206			`reg_status[1:1] = 0;`
207			`}`
208			`};`
209
210
211	132	creep	`update_n(arg : byte) is {`
212			`if (arg[7:7] == 1) {`
213			`reg_status[7:7] = 1;`
214			`}`
215			`else {`
216			`reg_status[7:7] = 0;`
217			`}`
218			`};`
219	131	creep	`};`
220			`'>`

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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Blame information for rev 155