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alu_chk.e
<'
import alu_components;
 
unit alu_chk_u {
        reg_a : byte;
        reg_x : byte;
        reg_y : byte;
        reg_status : byte;
        reg_result : byte;
 
        !inst : alu_input_s;
        !next_inst : alu_input_s;
 
        count_cycles : int;
        first_cycle : bool;
        last_a : byte;
        last_status : byte;
        last_result : byte;
 
        keep first_cycle == TRUE;
        keep count_cycles == 0;
 
        store(input : alu_input_s) is {
                count_cycles = count_cycles + 1;
 
                //out ("CYCLE ", count_cycles, " STORE:");
                //print input;
 
                last_a = reg_a;
                last_status = reg_status;
                last_result = reg_result;
 
                if (first_cycle) {
                        inst = input;
                        next_inst = input;
                }
                else {
                        inst = next_inst;
                        next_inst = input;
                };
 
        };
 
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
                if (first_cycle) {
                        first_cycle = FALSE;
                        reg_x = 0;
                        reg_y = 0;
                        reg_status = 8'b00100010;
                        reg_a = 0; // TODO: check this
                        reg_result = 0;
                }
                else {
                        //out ("CYCLE ", count_cycles, " COMPARE:");
                        //print inst;
 
                        if (count_cycles == 99999) {
                                out("ENOUGH!");
                                stop_run();
                        };
 
                        case inst.input_kind {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute();
                                };
                                DISABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": just comparing");
                                };
                                RESET: {
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_a = 0; // TODO: check this
                                        reg_result = 0;
 
                                        return;
                                };
                                default: {
                                        dut_error("error at e code");
                                };
                        };
 
                        // here i have already calculated. must compare!
 
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
                                out("#########################################################");
                                print me;
                                print me.inst;
                                out("#########################################################");
                                print alu_result;
                                print alu_status;
                                print alu_x;
                                print alu_y;
 
                                dut_error("WRONG!");
                        };
                };
        };
 
        execute() is {
                case inst.alu_opcode {
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                        ADC_ZPG: { exec_sum(); };
                        ADC_ZPX: { exec_sum(); };
                        ADC_ABS: { exec_sum(); };
                        ADC_ABX: { exec_sum(); };
                        ADC_ABY: { exec_sum(); };
                        ADC_IDX: { exec_sum(); };
                        ADC_IDY: { exec_sum(); };
 
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
                        AND_ZPG: { exec_and(); };
                        AND_ZPX: { exec_and(); };
                        AND_ABS: { exec_and(); };
                        AND_ABX: { exec_and(); };
                        AND_ABY: { exec_and(); };
                        AND_IDX: { exec_and(); };
                        AND_IDY: { exec_and(); };
 
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
 
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
                        ASL_ZPX: { exec_asl_mem(); };
                        ASL_ABS: { exec_asl_mem(); };
                        ASL_ABX: { exec_asl_mem(); };
 
                        BCC_REL: {}; // nothing is done. these are all branches.
                        BCS_REL: {};
                        BEQ_REL: {};
                        BMI_REL: {};
                        BNE_REL: {};
                        BPL_REL: {};
                        BVC_REL: {};
                        BVS_REL: {};
 
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
                        BIT_ABS: { exec_bit(); };
 
                        BRK_IMP: { reg_status[4:4] = 1; };
 
                        CLC_IMP: { reg_status[0:0] = 0; };
                        CLD_IMP: { reg_status[3:3] = 0; };
                        CLI_IMP: { reg_status[2:2] = 0; };
                        CLV_IMP: { reg_status[6:6] = 0; };
 
                        CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
                        CMP_ZPG: { exec_cmp(reg_a); };
                        CMP_ZPX: { exec_cmp(reg_a); };
                        CMP_ABS: { exec_cmp(reg_a); };
                        CMP_ABX: { exec_cmp(reg_a); };
                        CMP_ABY: { exec_cmp(reg_a); };
                        CMP_IDX: { exec_cmp(reg_a); };
                        CMP_IDY: { exec_cmp(reg_a); };
 
                        CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
                        CPX_ZPG: { exec_cmp(reg_x); };
                        CPX_ABS: { exec_cmp(reg_x); };
 
                        CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
                        CPY_ZPG: { exec_cmp(reg_y); };
                        CPY_ABS: { exec_cmp(reg_y); };
 
                        DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
                        DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
 
                        DEX_IMP: { exec_dec(reg_x, FALSE); };  // X,Z,N = X-1
                        DEY_IMP: { exec_dec(reg_y, FALSE); };  // Y,Z,N = Y-1
 
                        EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
                        EOR_ZPG: { exec_eor(); };
                        EOR_ZPX: { exec_eor(); };
                        EOR_ABS: { exec_eor(); };
                        EOR_ABX: { exec_eor(); };
                        EOR_ABY: { exec_eor(); };
                        EOR_IDX: { exec_eor(); };
                        EOR_IDY: { exec_eor(); };
 
                        INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
                        INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABS: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABX: { exec_inc(inst.alu_a, TRUE); };
 
                        INX_IMP: { exec_inc(reg_x, FALSE); };
                        INY_IMP: { exec_inc(reg_y, FALSE); };
 
                        JMP_ABS: {};
                        JMP_IND: {};
                        JSR_ABS: {};
 
                        LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
                        LDA_ZPG: { exec_load(reg_a, TRUE); };
                        LDA_ZPX: { exec_load(reg_a, TRUE); };
                        LDA_ABS: { exec_load(reg_a, TRUE); };
                        LDA_ABX: { exec_load(reg_a, TRUE); };
                        LDA_ABY: { exec_load(reg_a, TRUE); };
                        LDA_IDX: { exec_load(reg_a, TRUE); };
                        LDA_IDY: { exec_load(reg_a, TRUE); };
 
                        LDX_IMM: { exec_load(reg_x, FALSE); };
                        LDX_ZPG: { exec_load(reg_x, FALSE); };
                        LDX_ZPY: { exec_load(reg_x, FALSE); };
                        LDX_ABS: { exec_load(reg_x, FALSE); };
                        LDX_ABY: { exec_load(reg_x, FALSE); };
 
                        LDY_IMM: { exec_load(reg_y, FALSE); };
                        LDY_ZPG: { exec_load(reg_y, FALSE); };
                        LDY_ZPX: { exec_load(reg_y, FALSE); };
                        LDY_ABS: { exec_load(reg_y, FALSE); };
                        LDY_ABX: { exec_load(reg_y, FALSE); };
 
                        LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
                        LSR_ZPG: { exec_lsr(inst.alu_a); };
                        LSR_ZPX: { exec_lsr(inst.alu_a); };
                        LSR_ABS: { exec_lsr(inst.alu_a); };
                        LSR_ABX: { exec_lsr(inst.alu_a); };
 
                        NOP_IMP: {};
 
                        ORA_IMM: { exec_or(); }; // A,Z,N = A|M
                        ORA_ZPG: { exec_or(); };
                        ORA_ZPX: { exec_or(); };
                        ORA_ABS: { exec_or(); };
                        ORA_ABX: { exec_or(); };
                        ORA_ABY: { exec_or(); };
                        ORA_IDX: { exec_or(); };
                        ORA_IDY: { exec_or(); };
 
                        PHA_IMP: { reg_result = reg_a; };
                        PHP_IMP: {}; // P is always connected and the result is not updated
                        PLA_IMP: {
                                reg_a = inst.alu_a;
                                reg_result = inst.alu_a;
                                update_z(reg_a);
                                update_n(reg_a);
                        };
                        PLP_IMP: {
                                reg_status = inst.alu_a;
                                reg_status[5:5] = 1; // this is always one
                        };
 
                        ROL_ACC: { exec_rol(reg_a); };
                        ROL_ZPG: { exec_rol(inst.alu_a); };
                        ROL_ZPX: { exec_rol(inst.alu_a); };
                        ROL_ABS: { exec_rol(inst.alu_a); };
                        ROL_ABX: { exec_rol(inst.alu_a); };
 
                        default: {
                                out(inst.alu_opcode);
                                dut_error("unknown opcode");
                        }
                };
        };
 
        exec_rol(arg1 : *byte) is {
                var oldcarry : bit;
 
                oldcarry = reg_status[0:0];
                reg_status[0:0] = arg1[7:7];
                arg1 = arg1 << 1;
                arg1[0:0] = oldcarry;
 
                reg_result = arg1;
                update_z(arg1);
                update_n(arg1);
        };
 
        exec_or() is {
                reg_a = reg_a | inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_lsr(arg1 : *byte) is {
                reg_status[0:0] = arg1[0:0];
                arg1 = arg1 >> 1;
                update_z(arg1);
                update_n(arg1);
                reg_result = arg1;
        };
 
        exec_load(arg1 : *byte, update_result : bool) is {
                arg1 = inst.alu_a;
 
                if (update_result) { //
                        reg_result = inst.alu_a; // no need for this but...
                };
                update_z(arg1);
                update_n(arg1);
        };
 
        exec_inc(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 + 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { //
                        reg_result = arg1;
                };
        };
 
        exec_eor() is {
                reg_a = reg_a ^ inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_dec(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 - 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { // DEX and DEY do not output the result
                        reg_result = arg1;
                };
        };
 
        exec_cmp(arg1 : byte) is {
                update_z(arg1 - inst.alu_a);
                update_n(arg1 - inst.alu_a);
 
                if (arg1 >= inst.alu_a) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                };
        };
 
        exec_bit() is {
                update_z(reg_a & inst.alu_a);
                reg_status[7:7] = inst.alu_a[7:7];
                reg_status[6:6] = inst.alu_a[6:6];
        };
 
        exec_asl_acc() is {
                reg_status[0:0] = reg_a[7:7];
                reg_a = reg_a * 2;
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_asl_mem() is {
                reg_status[0:0] = inst.alu_a[7:7];
                reg_result = inst.alu_a * 2;
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_and() is {
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_sum() is {
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
                if (reg_status[3:3] == 1) {
                        var op1 : byte;
                        var op2 : byte;
 
                        out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
                        op1 = inst.alu_a[3:0];
                        op2 = inst.alu_a[7:4];
 
                        print op1;
                        print op2;
 
                        op1 = reg_a[3:0] + op1 + reg_status[0:0];
                        op2 = reg_a[7:4] + op2;
 
                        print op1;
                        print op2;
 
                        if (op1 >= 10) {
                                op2 = op2  + op1/ 10;
                                op1 = op1 % 10;
                        };
 
                        print op1;
                        print op2;
 
                        if (op2 >= 10) {
                                op2 = op2 % 10;
                                reg_status[0:0] = 1;
                        }
                        else {
                                reg_status[0:0] = 0;
                        };
 
                        reg_result[3:0] = op1;
                        reg_result[7:4] = op2;
                        update_z(reg_result);
                        update_n(reg_result);
                        reg_a = reg_result;
                }
                else {
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_z(reg_result);
                        update_n(reg_result);
                        reg_a = reg_result;
                };
        };
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
                if (arg1 + arg2 + arg3 > 255) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                }
        };
 
        update_v(op1 : byte, op2 : byte, res : byte) is {
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
                        reg_status[6:6] = 1;
                }
                else {
                        reg_status[6:6] = 0;
                };
        };
 
        update_z(arg : byte) is {
                if (arg == 0) {
                        reg_status[1:1] = 1;
                }
                else {
                        reg_status[1:1] = 0;
                }
        };
 
 
        update_n(arg : byte) is {
                if (arg[7:7] == 1) {
                        reg_status[7:7] = 1;
                }
                else {
                        reg_status[7:7] = 0;
                }
        };
};
'>

Line No.	Rev	Author	Line
1	131	creep	`alu_chk.e`
2			`<'`
3			`import alu_components;`
4
5			`unit alu_chk_u {`
6			`reg_a : byte;`
7			`reg_x : byte;`
8			`reg_y : byte;`
9			`reg_status : byte;`
10	135	creep	`reg_result : byte;`
11	131	creep
12	159	creep	`!inst : alu_input_s;`
13			`!next_inst : alu_input_s;`
14	132	creep
15	131	creep	`count_cycles : int;`
16			`first_cycle : bool;`
17	159	creep	`last_a : byte;`
18			`last_status : byte;`
19			`last_result : byte;`
20	131	creep
21			`keep first_cycle == TRUE;`
22			`keep count_cycles == 0;`
23
24			`store(input : alu_input_s) is {`
25	134	creep	`count_cycles = count_cycles + 1;`
26
27	153	creep	`//out ("CYCLE ", count_cycles, " STORE:");`
28			`//print input;`
29	132	creep
30	159	creep	`last_a = reg_a;`
31			`last_status = reg_status;`
32			`last_result = reg_result;`
33
34	132	creep	`if (first_cycle) {`
35			`inst = input;`
36			`next_inst = input;`
37			`}`
38			`else {`
39			`inst = next_inst;`
40			`next_inst = input;`
41			`};`
42
43	131	creep	`};`
44
45			`compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {`
46			`if (first_cycle) {`
47			`first_cycle = FALSE;`
48	143	creep	`reg_x = 0;`
49			`reg_y = 0;`
50			`reg_status = 8'b00100010;`
51	132	creep	`reg_a = 0; // TODO: check this`
52	135	creep	`reg_result = 0;`
53	131	creep	`}`
54	132	creep	`else {`
55	153	creep	`//out ("CYCLE ", count_cycles, " COMPARE:");`
56			`//print inst;`
57	134	creep
58	159	creep	`if (count_cycles == 99999) {`
59			`out("ENOUGH!");`
60			`stop_run();`
61			`};`
62
63	132	creep	`case inst.input_kind {`
64			`ENABLED_VALID: {`
65	153	creep	`//out("CYCLE ", count_cycles, ": executing and comparing");`
66	132	creep	`execute();`
67			`};`
68			`DISABLED_VALID: {`
69	153	creep	`//out("CYCLE ", count_cycles, ": just comparing");`
70	132	creep	`};`
71	143	creep	`RESET: {`
72	146	creep	`reg_x = 0;`
73			`reg_y = 0;`
74			`reg_status = 8'b00100010;`
75			`reg_a = 0; // TODO: check this`
76			`reg_result = 0;`
77
78	143	creep	`return;`
79			`};`
80	132	creep	`default: {`
81			`dut_error("error at e code");`
82			`};`
83			`};`
84
85	133	creep	`// here i have already calculated. must compare!`
86	143	creep
87	146	creep	`if ((reg_result != alu_result) \|\| (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {`
88	153	creep	`out("#########################################################");`
89	135	creep	`print me;`
90	155	creep	`print me.inst;`
91	153	creep	`out("#########################################################");`
92	134	creep	`print alu_result;`
93	135	creep	`print alu_status;`
94			`print alu_x;`
95			`print alu_y;`
96
97	133	creep	`dut_error("WRONG!");`
98			`};`
99	146	creep	`};`
100	131	creep	`};`
101	132	creep
102			`execute() is {`
103			`case inst.alu_opcode {`
104			`ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C`
105			`ADC_ZPG: { exec_sum(); };`
106			`ADC_ZPX: { exec_sum(); };`
107			`ADC_ABS: { exec_sum(); };`
108			`ADC_ABX: { exec_sum(); };`
109			`ADC_ABY: { exec_sum(); };`
110			`ADC_IDX: { exec_sum(); };`
111			`ADC_IDY: { exec_sum(); };`
112
113	133	creep	`AND_IMM: { exec_and(); }; // A,Z,N = A&M`
114	132	creep	`AND_ZPG: { exec_and(); };`
115			`AND_ZPX: { exec_and(); };`
116			`AND_ABS: { exec_and(); };`
117			`AND_ABX: { exec_and(); };`
118			`AND_ABY: { exec_and(); };`
119			`AND_IDX: { exec_and(); };`
120			`AND_IDY: { exec_and(); };`
121
122	135	creep	`ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2`
123	132	creep
124	135	creep	`ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2`
125			`ASL_ZPX: { exec_asl_mem(); };`
126			`ASL_ABS: { exec_asl_mem(); };`
127			`ASL_ABX: { exec_asl_mem(); };`
128
129	155	creep	`BCC_REL: {}; // nothing is done. these are all branches.`
130	153	creep	`BCS_REL: {};`
131			`BEQ_REL: {};`
132	155	creep	`BMI_REL: {};`
133			`BNE_REL: {};`
134			`BPL_REL: {};`
135			`BVC_REL: {};`
136			`BVS_REL: {};`
137	153	creep
138	155	creep	`BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6`
139			`BIT_ABS: { exec_bit(); };`
140
141			`BRK_IMP: { reg_status[4:4] = 1; };`
142
143			`CLC_IMP: { reg_status[0:0] = 0; };`
144			`CLD_IMP: { reg_status[3:3] = 0; };`
145			`CLI_IMP: { reg_status[2:2] = 0; };`
146			`CLV_IMP: { reg_status[6:6] = 0; };`
147
148	159	creep	`CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M`
149			`CMP_ZPG: { exec_cmp(reg_a); };`
150			`CMP_ZPX: { exec_cmp(reg_a); };`
151			`CMP_ABS: { exec_cmp(reg_a); };`
152			`CMP_ABX: { exec_cmp(reg_a); };`
153			`CMP_ABY: { exec_cmp(reg_a); };`
154			`CMP_IDX: { exec_cmp(reg_a); };`
155			`CMP_IDY: { exec_cmp(reg_a); };`
156
157			`CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M`
158			`CPX_ZPG: { exec_cmp(reg_x); };`
159			`CPX_ABS: { exec_cmp(reg_x); };`
160
161			`CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M`
162			`CPY_ZPG: { exec_cmp(reg_y); };`
163			`CPY_ABS: { exec_cmp(reg_y); };`
164
165			`DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1`
166			`DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };`
167			`DEC_ABS: { exec_dec(inst.alu_a, TRUE); };`
168			`DEC_ABX: { exec_dec(inst.alu_a, TRUE); };`
169
170			`DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1`
171			`DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1`
172
173			`EOR_IMM: { exec_eor(); }; // A,Z,N = A^M`
174			`EOR_ZPG: { exec_eor(); };`
175			`EOR_ZPX: { exec_eor(); };`
176			`EOR_ABS: { exec_eor(); };`
177			`EOR_ABX: { exec_eor(); };`
178			`EOR_ABY: { exec_eor(); };`
179			`EOR_IDX: { exec_eor(); };`
180			`EOR_IDY: { exec_eor(); };`
181
182			`INC_ZPG: { exec_inc(inst.alu_a, TRUE); };`
183			`INC_ZPX: { exec_inc(inst.alu_a, TRUE); };`
184			`INC_ABS: { exec_inc(inst.alu_a, TRUE); };`
185			`INC_ABX: { exec_inc(inst.alu_a, TRUE); };`
186
187			`INX_IMP: { exec_inc(reg_x, FALSE); };`
188			`INY_IMP: { exec_inc(reg_y, FALSE); };`
189
190			`JMP_ABS: {};`
191			`JMP_IND: {};`
192			`JSR_ABS: {};`
193
194			`LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M`
195			`LDA_ZPG: { exec_load(reg_a, TRUE); };`
196			`LDA_ZPX: { exec_load(reg_a, TRUE); };`
197			`LDA_ABS: { exec_load(reg_a, TRUE); };`
198			`LDA_ABX: { exec_load(reg_a, TRUE); };`
199			`LDA_ABY: { exec_load(reg_a, TRUE); };`
200			`LDA_IDX: { exec_load(reg_a, TRUE); };`
201			`LDA_IDY: { exec_load(reg_a, TRUE); };`
202
203			`LDX_IMM: { exec_load(reg_x, FALSE); };`
204			`LDX_ZPG: { exec_load(reg_x, FALSE); };`
205			`LDX_ZPY: { exec_load(reg_x, FALSE); };`
206			`LDX_ABS: { exec_load(reg_x, FALSE); };`
207			`LDX_ABY: { exec_load(reg_x, FALSE); };`
208
209			`LDY_IMM: { exec_load(reg_y, FALSE); };`
210			`LDY_ZPG: { exec_load(reg_y, FALSE); };`
211			`LDY_ZPX: { exec_load(reg_y, FALSE); };`
212			`LDY_ABS: { exec_load(reg_y, FALSE); };`
213			`LDY_ABX: { exec_load(reg_y, FALSE); };`
214
215			`LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2`
216			`LSR_ZPG: { exec_lsr(inst.alu_a); };`
217			`LSR_ZPX: { exec_lsr(inst.alu_a); };`
218			`LSR_ABS: { exec_lsr(inst.alu_a); };`
219			`LSR_ABX: { exec_lsr(inst.alu_a); };`
220
221			`NOP_IMP: {};`
222
223			`ORA_IMM: { exec_or(); }; // A,Z,N = A\|M`
224			`ORA_ZPG: { exec_or(); };`
225			`ORA_ZPX: { exec_or(); };`
226			`ORA_ABS: { exec_or(); };`
227			`ORA_ABX: { exec_or(); };`
228			`ORA_ABY: { exec_or(); };`
229			`ORA_IDX: { exec_or(); };`
230			`ORA_IDY: { exec_or(); };`
231
232			`PHA_IMP: { reg_result = reg_a; };`
233			`PHP_IMP: {}; // P is always connected and the result is not updated`
234			`PLA_IMP: {`
235			`reg_a = inst.alu_a;`
236			`reg_result = inst.alu_a;`
237			`update_z(reg_a);`
238			`update_n(reg_a);`
239			`};`
240			`PLP_IMP: {`
241			`reg_status = inst.alu_a;`
242			`reg_status[5:5] = 1; // this is always one`
243			`};`
244
245	170	creep	`ROL_ACC: { exec_rol(reg_a); };`
246			`ROL_ZPG: { exec_rol(inst.alu_a); };`
247			`ROL_ZPX: { exec_rol(inst.alu_a); };`
248			`ROL_ABS: { exec_rol(inst.alu_a); };`
249			`ROL_ABX: { exec_rol(inst.alu_a); };`
250	160	creep
251	132	creep	`default: {`
252	155	creep	`out(inst.alu_opcode);`
253			`dut_error("unknown opcode");`
254	132	creep	`}`
255			`};`
256			`};`
257
258	160	creep	`exec_rol(arg1 : *byte) is {`
259			`var oldcarry : bit;`
260
261			`oldcarry = reg_status[0:0];`
262			`reg_status[0:0] = arg1[7:7];`
263			`arg1 = arg1 << 1;`
264			`arg1[0:0] = oldcarry;`
265
266	170	creep	`reg_result = arg1;`
267			`update_z(arg1);`
268			`update_n(arg1);`
269	160	creep	`};`
270
271	159	creep	`exec_or() is {`
272			`reg_a = reg_a \| inst.alu_a;`
273			`reg_result = reg_a;`
274			`update_z(reg_a);`
275			`update_n(reg_a);`
276			`};`
277
278			`exec_lsr(arg1 : *byte) is {`
279			`reg_status[0:0] = arg1[0:0];`
280			`arg1 = arg1 >> 1;`
281			`update_z(arg1);`
282			`update_n(arg1);`
283			`reg_result = arg1;`
284			`};`
285
286			`exec_load(arg1 : *byte, update_result : bool) is {`
287			`arg1 = inst.alu_a;`
288
289			`if (update_result) { //`
290			`reg_result = inst.alu_a; // no need for this but...`
291			`};`
292			`update_z(arg1);`
293			`update_n(arg1);`
294			`};`
295
296			`exec_inc(arg1 : *byte, update_result : bool) is {`
297			`arg1 = arg1 + 1;`
298			`update_z(arg1);`
299			`update_n(arg1);`
300
301			`if (update_result) { //`
302			`reg_result = arg1;`
303			`};`
304			`};`
305
306			`exec_eor() is {`
307			`reg_a = reg_a ^ inst.alu_a;`
308			`reg_result = reg_a;`
309			`update_z(reg_a);`
310			`update_n(reg_a);`
311			`};`
312
313			`exec_dec(arg1 : *byte, update_result : bool) is {`
314			`arg1 = arg1 - 1;`
315			`update_z(arg1);`
316			`update_n(arg1);`
317
318			`if (update_result) { // DEX and DEY do not output the result`
319			`reg_result = arg1;`
320			`};`
321			`};`
322
323			`exec_cmp(arg1 : byte) is {`
324			`update_z(arg1 - inst.alu_a);`
325			`update_n(arg1 - inst.alu_a);`
326
327			`if (arg1 >= inst.alu_a) {`
328			`reg_status[0:0] = 1;`
329			`}`
330			`else {`
331			`reg_status[0:0] = 0;`
332			`};`
333			`};`
334
335	155	creep	`exec_bit() is {`
336			`update_z(reg_a & inst.alu_a);`
337			`reg_status[7:7] = inst.alu_a[7:7];`
338			`reg_status[6:6] = inst.alu_a[6:6];`
339			`};`
340
341	135	creep	`exec_asl_acc() is {`
342			`reg_status[0:0] = reg_a[7:7];`
343			`reg_a = reg_a * 2;`
344			`update_z(reg_a);`
345			`update_n(reg_a);`
346			`reg_result = reg_a;`
347			`};`
348
349			`exec_asl_mem() is {`
350			`reg_status[0:0] = inst.alu_a[7:7];`
351			`reg_result = inst.alu_a * 2;`
352			`update_z(reg_result);`
353			`update_n(reg_result);`
354			`};`
355
356	132	creep	`exec_and() is {`
357	133	creep	`reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong`
358			`update_z(reg_a);`
359			`update_n(reg_a);`
360	135	creep	`reg_result = reg_a;`
361	132	creep	`};`
362
363			`exec_sum() is {`
364	153	creep	`//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);`
365	160	creep	`if (reg_status[3:3] == 1) {`
366			`var op1 : byte;`
367			`var op2 : byte;`
368
369	170	creep	`out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);`
370
371	160	creep	`op1 = inst.alu_a[3:0];`
372			`op2 = inst.alu_a[7:4];`
373
374			`print op1;`
375			`print op2;`
376
377			`op1 = reg_a[3:0] + op1 + reg_status[0:0];`
378			`op2 = reg_a[7:4] + op2;`
379
380	170	creep	`print op1;`
381			`print op2;`
382
383	160	creep	`if (op1 >= 10) {`
384	170	creep	`op2 = op2 + op1/ 10;`
385	160	creep	`op1 = op1 % 10;`
386			`};`
387	170	creep
388			`print op1;`
389			`print op2;`
390	160	creep
391			`if (op2 >= 10) {`
392			`op2 = op2 % 10;`
393			`reg_status[0:0] = 1;`
394			`}`
395			`else {`
396			`reg_status[0:0] = 0;`
397			`};`
398
399			`reg_result[3:0] = op1;`
400			`reg_result[7:4] = op2;`
401			`update_z(reg_result);`
402			`update_n(reg_result);`
403			`reg_a = reg_result;`
404			`}`
405			`else {`
406			`reg_result = reg_a + inst.alu_a + reg_status[0:0];`
407			`update_c(reg_a, inst.alu_a, reg_status[0:0]);`
408			`update_v(reg_a, inst.alu_a, reg_result);`
409			`update_z(reg_result);`
410			`update_n(reg_result);`
411			`reg_a = reg_result;`
412			`};`
413	132	creep	`};`
414
415	143	creep	`update_c(arg1 : byte, arg2 : byte, arg3: bit) is {`
416	153	creep	`if (arg1 + arg2 + arg3 > 255) {`
417	132	creep	`reg_status[0:0] = 1;`
418			`}`
419			`else {`
420			`reg_status[0:0] = 0;`
421			`}`
422			`};`
423
424	146	creep	`update_v(op1 : byte, op2 : byte, res : byte) is {`
425			`if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {`
426			`reg_status[6:6] = 1;`
427			`}`
428			`else {`
429			`reg_status[6:6] = 0;`
430			`};`
431			`};`
432
433			`update_z(arg : byte) is {`
434			`if (arg == 0) {`
435			`reg_status[1:1] = 1;`
436			`}`
437			`else {`
438			`reg_status[1:1] = 0;`
439			`}`
440			`};`
441
442
443	132	creep	`update_n(arg : byte) is {`
444			`if (arg[7:7] == 1) {`
445			`reg_status[7:7] = 1;`
446			`}`
447			`else {`
448			`reg_status[7:7] = 0;`
449			`}`
450			`};`
451	131	creep	`};`
452			`'>`

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