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alu_chk.e
<'
import alu_components;
 
unit alu_chk_u {
        reg_a : byte;
        reg_x : byte;
        reg_y : byte;
        reg_status : byte;
        reg_result : byte;
 
        !inst : alu_input_s;
        !next_inst : alu_input_s;
 
        count_cycles : int;
        first_cycle : bool;
        last_a : byte;
        last_status : byte;
        last_result : byte;
        rst_counter : byte;
 
        keep first_cycle == TRUE;
        keep count_cycles == 0;
        keep rst_counter == 0;
 
        event T3_cover_event;
        cover T3_cover_event is {
                item rst_counter; // using num_of_buckets=100;
        };
 
 
        store(input : alu_input_s) is {
                count_cycles = count_cycles + 1;
 
                //out ("CYCLE ", count_cycles, " STORE:");
                //print input;
 
                last_a = reg_a;
                last_status = reg_status;
                last_result = reg_result;
 
                if (first_cycle) {
                        inst = input;
                        next_inst = input;
                }
                else {
                        inst = next_inst;
                        next_inst = input;
                };
 
        };
 
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
                if (first_cycle) {
                        first_cycle = FALSE;
                        reg_x = 0;
                        reg_y = 0;
                        reg_status = 8'b00100010;
                        reg_a = 0;
                        reg_result = 0;
                }
                else {
                        //out ("CYCLE ", count_cycles, " COMPARE:");
                        //print inst;
 
                        if (count_cycles == 99999) {
                                out("ENOUGH!");
                                stop_run();
                        };
 
                        if (inst.input_kind == RESET) {
                                rst_counter = rst_counter + 1;
                        }
                        else {
                                emit T3_cover_event;
                                rst_counter = 0;
                        };
 
                        case inst.input_kind {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute(inst.alu_opcode);
 
                                        if (reg_status[3:3] == 1) {
                                                case inst.alu_opcode {
                                                        SBC_IMM: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPG: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABS: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                };
                                        };
                                };
                                RESET: {
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_a = 0; // TODO: check this
                                        reg_result = 0;
 
                                        return;
                                };
                                ENABLED_RAND: {
                                        execute(inst.rand_op.as_a(valid_opcodes));
 
                                        if (reg_status[3:3] == 1) {
                                                case inst.rand_op.as_a(valid_opcodes) {
                                                        SBC_IMM: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPG: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABS: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                };
                                        };
 
                                };
                                default: {
                                };
                        };
 
                        // here i have already calculated. must compare!
 
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
                                out("#########################################################");
                                print me;
                                print me.inst;
                                out("#########################################################");
                                print alu_result;
                                print alu_status;
                                print alu_x;
                                print alu_y;
 
                                dut_error("WRONG!");
                        };
                };
        };
 
        execute(opcode : valid_opcodes) is {
                case opcode {
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                        ADC_ZPG: { exec_sum(); };
                        ADC_ZPX: { exec_sum(); };
                        ADC_ABS: { exec_sum(); };
                        ADC_ABX: { exec_sum(); };
                        ADC_ABY: { exec_sum(); };
                        ADC_IDX: { exec_sum(); };
                        ADC_IDY: { exec_sum(); };
 
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
                        AND_ZPG: { exec_and(); };
                        AND_ZPX: { exec_and(); };
                        AND_ABS: { exec_and(); };
                        AND_ABX: { exec_and(); };
                        AND_ABY: { exec_and(); };
                        AND_IDX: { exec_and(); };
                        AND_IDY: { exec_and(); };
 
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
 
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
                        ASL_ZPX: { exec_asl_mem(); };
                        ASL_ABS: { exec_asl_mem(); };
                        ASL_ABX: { exec_asl_mem(); };
 
                        BCC_REL: {}; // nothing is done. these are all branches.
                        BCS_REL: {};
                        BEQ_REL: {};
                        BMI_REL: {};
                        BNE_REL: {};
                        BPL_REL: {};
                        BVC_REL: {};
                        BVS_REL: {};
 
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
                        BIT_ABS: { exec_bit(); };
 
                        BRK_IMP: { reg_status[4:4] = 1; };
 
                        CLC_IMP: { reg_status[0:0] = 0; };
                        CLD_IMP: { reg_status[3:3] = 0; };
                        CLI_IMP: { reg_status[2:2] = 0; };
                        CLV_IMP: { reg_status[6:6] = 0; };
 
                        CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
                        CMP_ZPG: { exec_cmp(reg_a); };
                        CMP_ZPX: { exec_cmp(reg_a); };
                        CMP_ABS: { exec_cmp(reg_a); };
                        CMP_ABX: { exec_cmp(reg_a); };
                        CMP_ABY: { exec_cmp(reg_a); };
                        CMP_IDX: { exec_cmp(reg_a); };
                        CMP_IDY: { exec_cmp(reg_a); };
 
                        CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
                        CPX_ZPG: { exec_cmp(reg_x); };
                        CPX_ABS: { exec_cmp(reg_x); };
 
                        CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
                        CPY_ZPG: { exec_cmp(reg_y); };
                        CPY_ABS: { exec_cmp(reg_y); };
 
                        DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
                        DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
 
                        DEX_IMP: { exec_dec(reg_x, FALSE); };  // X,Z,N = X-1
                        DEY_IMP: { exec_dec(reg_y, FALSE); };  // Y,Z,N = Y-1
 
                        EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
                        EOR_ZPG: { exec_eor(); };
                        EOR_ZPX: { exec_eor(); };
                        EOR_ABS: { exec_eor(); };
                        EOR_ABX: { exec_eor(); };
                        EOR_ABY: { exec_eor(); };
                        EOR_IDX: { exec_eor(); };
                        EOR_IDY: { exec_eor(); };
 
                        INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
                        INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABS: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABX: { exec_inc(inst.alu_a, TRUE); };
 
                        INX_IMP: { exec_inc(reg_x, FALSE); };
                        INY_IMP: { exec_inc(reg_y, FALSE); };
 
                        JMP_ABS: {};
                        JMP_IND: {};
                        JSR_ABS: {};
 
                        LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
                        LDA_ZPG: { exec_load(reg_a, TRUE); };
                        LDA_ZPX: { exec_load(reg_a, TRUE); };
                        LDA_ABS: { exec_load(reg_a, TRUE); };
                        LDA_ABX: { exec_load(reg_a, TRUE); };
                        LDA_ABY: { exec_load(reg_a, TRUE); };
                        LDA_IDX: { exec_load(reg_a, TRUE); };
                        LDA_IDY: { exec_load(reg_a, TRUE); };
 
                        LDX_IMM: { exec_load(reg_x, FALSE); };
                        LDX_ZPG: { exec_load(reg_x, FALSE); };
                        LDX_ZPY: { exec_load(reg_x, FALSE); };
                        LDX_ABS: { exec_load(reg_x, FALSE); };
                        LDX_ABY: { exec_load(reg_x, FALSE); };
 
                        LDY_IMM: { exec_load(reg_y, FALSE); };
                        LDY_ZPG: { exec_load(reg_y, FALSE); };
                        LDY_ZPX: { exec_load(reg_y, FALSE); };
                        LDY_ABS: { exec_load(reg_y, FALSE); };
                        LDY_ABX: { exec_load(reg_y, FALSE); };
 
                        LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
                        LSR_ZPG: { exec_lsr(inst.alu_a); };
                        LSR_ZPX: { exec_lsr(inst.alu_a); };
                        LSR_ABS: { exec_lsr(inst.alu_a); };
                        LSR_ABX: { exec_lsr(inst.alu_a); };
 
                        NOP_IMP: {};
 
                        ORA_IMM: { exec_or(); }; // A,Z,N = A|M
                        ORA_ZPG: { exec_or(); };
                        ORA_ZPX: { exec_or(); };
                        ORA_ABS: { exec_or(); };
                        ORA_ABX: { exec_or(); };
                        ORA_ABY: { exec_or(); };
                        ORA_IDX: { exec_or(); };
                        ORA_IDY: { exec_or(); };
 
                        PHA_IMP: { reg_result = reg_a; };
                        PHP_IMP: {}; // P is always connected and the result is not updated
                        PLA_IMP: {
                                reg_a = inst.alu_a;
                                reg_result = inst.alu_a;
                                update_z(reg_a);
                                update_n(reg_a);
                        };
                        PLP_IMP: {
                                reg_status = inst.alu_a;
                                reg_status[5:5] = 1; // this is always one
                        };
 
                        ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
                        ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
                        ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
                        ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
 
                        RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
                        RTS_IMP: { };
 
                        SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
                        SBC_ZPG: { exec_sub(); };
                        SBC_ZPX: { exec_sub(); };
                        SBC_ABS: { exec_sub(); };
                        SBC_ABX: { exec_sub(); };
                        SBC_ABY: { exec_sub(); };
                        SBC_IDX: { exec_sub(); };
                        SBC_IDY: { exec_sub(); };
 
                        SEC_IMP: { reg_status[0:0] = 1; };
                        SED_IMP: { reg_status[3:3] = 1; };
                        SEI_IMP: { reg_status[2:2] = 1; };
 
                        STA_ZPG: { reg_result = reg_a; };
                        STA_ZPX: { reg_result = reg_a; };
                        STA_ABS: { reg_result = reg_a; };
                        STA_ABX: { reg_result = reg_a; };
                        STA_ABY: { reg_result = reg_a; };
                        STA_IDX: { reg_result = reg_a; };
                        STA_IDY: { reg_result = reg_a; };
                        STX_ZPG: { };
                        STX_ZPY: { };
                        STX_ABS: { };
                        STY_ZPG: { };
                        STY_ZPX: { };
                        STY_ABS: { };
 
                        TAX_IMP: { exec_transfer(reg_a, reg_x); };
                        TAY_IMP: { exec_transfer(reg_a, reg_y); };
                        TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
                        TXA_IMP: { exec_transfer(reg_x, reg_a); };
                        TXS_IMP: { };
                        TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
 
                        // note: tya and txa do not update the result register
 
                        default: {
                                // all the random generated opcodes will fall here
                        }
                };
        };
 
        exec_transfer(source : byte, dest : *byte) is {
                dest = source;
                update_z(dest);
                update_n(dest);
        };
 
        exec_sub() is {
                if (reg_status[3:3] == 1) {
                        var op1 : int;
                        var op2 : int;
 
                        warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
 
                        //out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
                        op1 = inst.alu_a[3:0];
                        op2 = inst.alu_a[7:4];
 
                        op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
                        op2 = reg_a[7:4] - op2;
 
                        if (op1 >= 10) {
                                op2 = op2  + op1/10;
                                op1 = op1 % 10;
                        } else if (op1 < 0) {
                                op2 = op2 - op1/10;
                                op1 = -(op1 % 10);
                        };
 
                        reg_status[0:0] = 1;
 
                        if (op2 >= 10) {
                                op2 = op2 % 10;
                        }
                        else if (op2 < 0) {
                                op2 = op2 + 10;
                                reg_status[0:0] = 0;
                        };
 
                        reg_result[3:0] = op1;
                        reg_result[7:4] = op2;
                }
                else {
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        if (reg_result[7:7] == 1) {
                                reg_status[0:0] = 0;
                        }
                        else {
                                reg_status[0:0] = 1;
                        };
                };
 
                update_z(reg_result);
                update_n(reg_result);
                update_v(reg_a, inst.alu_a, reg_result);
 
 
                reg_a = reg_result;
 
        };
 
        exec_rot(left : bool, arg1 : byte) is {
                var oldcarry : bit;
 
                if (left) {
                        oldcarry = reg_status[0:0];
                        reg_status[0:0] = arg1[7:7];
                        reg_result = arg1 << 1;
                        reg_result[0:0] = oldcarry;
                }
                else {
                        oldcarry = reg_status[0:0];
                        reg_status[0:0] = arg1[0:0];
                        reg_result = arg1 >> 1;
                        reg_result[7:7] = oldcarry;
                };
 
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_or() is {
                reg_a = reg_a | inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_lsr(arg1 : *byte) is {
                reg_status[0:0] = arg1[0:0];
                arg1 = arg1 >> 1;
                update_z(arg1);
                update_n(arg1);
                reg_result = arg1;
        };
 
        exec_load(arg1 : *byte, update_result : bool) is {
                arg1 = inst.alu_a;
 
                if (update_result) { //
                        reg_result = inst.alu_a; // no need for this but...
                };
                update_z(arg1);
                update_n(arg1);
        };
 
        exec_inc(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 + 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { //
                        reg_result = arg1;
                };
        };
 
        exec_eor() is {
                reg_a = reg_a ^ inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_dec(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 - 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { // DEX and DEY do not output the result
                        reg_result = arg1;
                };
        };
 
        exec_cmp(arg1 : byte) is {
                update_z(arg1 - inst.alu_a);
                update_n(arg1 - inst.alu_a);
 
                if (arg1 >= inst.alu_a) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                };
        };
 
        exec_bit() is {
                update_z(reg_a & inst.alu_a);
                reg_status[7:7] = inst.alu_a[7:7];
                reg_status[6:6] = inst.alu_a[6:6];
        };
 
        exec_asl_acc() is {
                reg_status[0:0] = reg_a[7:7];
                reg_a = reg_a * 2;
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_asl_mem() is {
                reg_status[0:0] = inst.alu_a[7:7];
                reg_result = inst.alu_a * 2;
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_and() is {
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_sum() is {
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
                if (reg_status[3:3] == 1) {
                        var op1 : byte;
                        var op2 : byte;
 
                        //out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
 
                        op1 = inst.alu_a[3:0];
                        op2 = inst.alu_a[7:4];
 
                        op1 = reg_a[3:0] + op1 + reg_status[0:0];
                        op2 = reg_a[7:4] + op2;
 
                        if (op1 >= 10) {
                                op2 = op2  + op1/ 10;
                                op1 = op1 % 10;
                        };
 
                        if (op2 >= 10) {
                                op2 = op2 % 10;
                                reg_status[0:0] = 1;
                        }
                        else {
                                reg_status[0:0] = 0;
                        };
 
                        reg_result[3:0] = op1;
                        reg_result[7:4] = op2;
                        update_z(reg_result);
                        update_n(reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        reg_a = reg_result;
                }
                else {
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_z(reg_result);
                        update_n(reg_result);
                        reg_a = reg_result;
                };
        };
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
                if (arg1 + arg2 + arg3 > 255) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                }
        };
 
        update_v(op1 : byte, op2 : byte, res : byte) is {
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
                        reg_status[6:6] = 1;
                }
                else {
                        reg_status[6:6] = 0;
                };
        };
 
        update_z(arg : byte) is {
                if (arg == 0) {
                        reg_status[1:1] = 1;
                }
                else {
                        reg_status[1:1] = 0;
                }
        };
 
 
        update_n(arg : byte) is {
                if (arg[7:7] == 1) {
                        reg_status[7:7] = 1;
                }
                else {
                        reg_status[7:7] = 0;
                }
        };
};
'>

Line No.	Rev	Author	Line
1	131	creep	`alu_chk.e`
2			`<'`
3			`import alu_components;`
4
5			`unit alu_chk_u {`
6			`reg_a : byte;`
7			`reg_x : byte;`
8			`reg_y : byte;`
9			`reg_status : byte;`
10	135	creep	`reg_result : byte;`
11	131	creep
12	159	creep	`!inst : alu_input_s;`
13			`!next_inst : alu_input_s;`
14	132	creep
15	131	creep	`count_cycles : int;`
16			`first_cycle : bool;`
17	159	creep	`last_a : byte;`
18			`last_status : byte;`
19			`last_result : byte;`
20	182	creep	`rst_counter : byte;`
21	131	creep
22			`keep first_cycle == TRUE;`
23			`keep count_cycles == 0;`
24	182	creep	`keep rst_counter == 0;`
25	131	creep
26	182	creep	`event T3_cover_event;`
27			`cover T3_cover_event is {`
28			`item rst_counter; // using num_of_buckets=100;`
29			`};`
30
31
32	131	creep	`store(input : alu_input_s) is {`
33	134	creep	`count_cycles = count_cycles + 1;`
34
35	153	creep	`//out ("CYCLE ", count_cycles, " STORE:");`
36			`//print input;`
37	132	creep
38	159	creep	`last_a = reg_a;`
39			`last_status = reg_status;`
40			`last_result = reg_result;`
41
42	132	creep	`if (first_cycle) {`
43			`inst = input;`
44			`next_inst = input;`
45			`}`
46			`else {`
47			`inst = next_inst;`
48			`next_inst = input;`
49			`};`
50
51	131	creep	`};`
52
53			`compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {`
54			`if (first_cycle) {`
55			`first_cycle = FALSE;`
56	143	creep	`reg_x = 0;`
57			`reg_y = 0;`
58			`reg_status = 8'b00100010;`
59	185	creep	`reg_a = 0;`
60	135	creep	`reg_result = 0;`
61	131	creep	`}`
62	132	creep	`else {`
63	185	creep	`//out ("CYCLE ", count_cycles, " COMPARE:");`
64			`//print inst;`
65	134	creep
66	159	creep	`if (count_cycles == 99999) {`
67			`out("ENOUGH!");`
68			`stop_run();`
69			`};`
70
71	182	creep	`if (inst.input_kind == RESET) {`
72			`rst_counter = rst_counter + 1;`
73			`}`
74			`else {`
75			`emit T3_cover_event;`
76			`rst_counter = 0;`
77			`};`
78
79	132	creep	`case inst.input_kind {`
80			`ENABLED_VALID: {`
81	153	creep	`//out("CYCLE ", count_cycles, ": executing and comparing");`
82	185	creep	`execute(inst.alu_opcode);`
83
84			`if (reg_status[3:3] == 1) {`
85			`case inst.alu_opcode {`
86			`SBC_IMM: {`
87			`reg_a = alu_result;`
88			`reg_result = alu_result;`
89			`reg_status = alu_status;`
90			`};`
91			`SBC_ZPG: {`
92			`reg_a = alu_result;`
93			`reg_result = alu_result;`
94			`reg_status = alu_status;`
95			`};`
96			`SBC_ZPX: {`
97			`reg_a = alu_result;`
98			`reg_result = alu_result;`
99			`reg_status = alu_status;`
100			`};`
101			`SBC_ABS: {`
102			`reg_a = alu_result;`
103			`reg_result = alu_result;`
104			`reg_status = alu_status;`
105			`};`
106			`SBC_ABX: {`
107			`reg_a = alu_result;`
108			`reg_result = alu_result;`
109			`reg_status = alu_status;`
110			`};`
111			`SBC_ABY: {`
112			`reg_a = alu_result;`
113			`reg_result = alu_result;`
114			`reg_status = alu_status;`
115			`};`
116			`SBC_IDX: {`
117			`reg_a = alu_result;`
118			`reg_result = alu_result;`
119			`reg_status = alu_status;`
120			`};`
121			`SBC_IDY: {`
122			`reg_a = alu_result;`
123			`reg_result = alu_result;`
124			`reg_status = alu_status;`
125			`};`
126			`};`
127			`};`
128	132	creep	`};`
129	143	creep	`RESET: {`
130	146	creep	`reg_x = 0;`
131			`reg_y = 0;`
132			`reg_status = 8'b00100010;`
133			`reg_a = 0; // TODO: check this`
134			`reg_result = 0;`
135
136	143	creep	`return;`
137			`};`
138	182	creep	`ENABLED_RAND: {`
139	185	creep	`execute(inst.rand_op.as_a(valid_opcodes));`
140
141			`if (reg_status[3:3] == 1) {`
142			`case inst.rand_op.as_a(valid_opcodes) {`
143			`SBC_IMM: {`
144			`reg_a = alu_result;`
145			`reg_result = alu_result;`
146			`reg_status = alu_status;`
147			`};`
148			`SBC_ZPG: {`
149			`reg_a = alu_result;`
150			`reg_result = alu_result;`
151			`reg_status = alu_status;`
152			`};`
153			`SBC_ZPX: {`
154			`reg_a = alu_result;`
155			`reg_result = alu_result;`
156			`reg_status = alu_status;`
157			`};`
158			`SBC_ABS: {`
159			`reg_a = alu_result;`
160			`reg_result = alu_result;`
161			`reg_status = alu_status;`
162			`};`
163			`SBC_ABX: {`
164			`reg_a = alu_result;`
165			`reg_result = alu_result;`
166			`reg_status = alu_status;`
167			`};`
168			`SBC_ABY: {`
169			`reg_a = alu_result;`
170			`reg_result = alu_result;`
171			`reg_status = alu_status;`
172			`};`
173			`SBC_IDX: {`
174			`reg_a = alu_result;`
175			`reg_result = alu_result;`
176			`reg_status = alu_status;`
177			`};`
178			`SBC_IDY: {`
179			`reg_a = alu_result;`
180			`reg_result = alu_result;`
181			`reg_status = alu_status;`
182			`};`
183			`};`
184			`};`
185
186	182	creep	`};`
187	132	creep	`default: {`
188			`};`
189			`};`
190
191	133	creep	`// here i have already calculated. must compare!`
192	143	creep
193	146	creep	`if ((reg_result != alu_result) \|\| (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {`
194	153	creep	`out("#########################################################");`
195	135	creep	`print me;`
196	155	creep	`print me.inst;`
197	153	creep	`out("#########################################################");`
198	134	creep	`print alu_result;`
199	135	creep	`print alu_status;`
200			`print alu_x;`
201			`print alu_y;`
202
203	133	creep	`dut_error("WRONG!");`
204			`};`
205	146	creep	`};`
206	131	creep	`};`
207	132	creep
208	185	creep	`execute(opcode : valid_opcodes) is {`
209			`case opcode {`
210	132	creep	`ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C`
211			`ADC_ZPG: { exec_sum(); };`
212			`ADC_ZPX: { exec_sum(); };`
213			`ADC_ABS: { exec_sum(); };`
214			`ADC_ABX: { exec_sum(); };`
215			`ADC_ABY: { exec_sum(); };`
216			`ADC_IDX: { exec_sum(); };`
217			`ADC_IDY: { exec_sum(); };`
218
219	133	creep	`AND_IMM: { exec_and(); }; // A,Z,N = A&M`
220	132	creep	`AND_ZPG: { exec_and(); };`
221			`AND_ZPX: { exec_and(); };`
222			`AND_ABS: { exec_and(); };`
223			`AND_ABX: { exec_and(); };`
224			`AND_ABY: { exec_and(); };`
225			`AND_IDX: { exec_and(); };`
226			`AND_IDY: { exec_and(); };`
227
228	135	creep	`ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2`
229	132	creep
230	135	creep	`ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2`
231			`ASL_ZPX: { exec_asl_mem(); };`
232			`ASL_ABS: { exec_asl_mem(); };`
233			`ASL_ABX: { exec_asl_mem(); };`
234
235	155	creep	`BCC_REL: {}; // nothing is done. these are all branches.`
236	153	creep	`BCS_REL: {};`
237			`BEQ_REL: {};`
238	155	creep	`BMI_REL: {};`
239			`BNE_REL: {};`
240			`BPL_REL: {};`
241			`BVC_REL: {};`
242			`BVS_REL: {};`
243	153	creep
244	155	creep	`BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6`
245			`BIT_ABS: { exec_bit(); };`
246
247			`BRK_IMP: { reg_status[4:4] = 1; };`
248
249			`CLC_IMP: { reg_status[0:0] = 0; };`
250			`CLD_IMP: { reg_status[3:3] = 0; };`
251			`CLI_IMP: { reg_status[2:2] = 0; };`
252			`CLV_IMP: { reg_status[6:6] = 0; };`
253
254	159	creep	`CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M`
255			`CMP_ZPG: { exec_cmp(reg_a); };`
256			`CMP_ZPX: { exec_cmp(reg_a); };`
257			`CMP_ABS: { exec_cmp(reg_a); };`
258			`CMP_ABX: { exec_cmp(reg_a); };`
259			`CMP_ABY: { exec_cmp(reg_a); };`
260			`CMP_IDX: { exec_cmp(reg_a); };`
261			`CMP_IDY: { exec_cmp(reg_a); };`
262
263			`CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M`
264			`CPX_ZPG: { exec_cmp(reg_x); };`
265			`CPX_ABS: { exec_cmp(reg_x); };`
266
267			`CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M`
268			`CPY_ZPG: { exec_cmp(reg_y); };`
269			`CPY_ABS: { exec_cmp(reg_y); };`
270
271			`DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1`
272			`DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };`
273			`DEC_ABS: { exec_dec(inst.alu_a, TRUE); };`
274			`DEC_ABX: { exec_dec(inst.alu_a, TRUE); };`
275
276			`DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1`
277			`DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1`
278
279			`EOR_IMM: { exec_eor(); }; // A,Z,N = A^M`
280			`EOR_ZPG: { exec_eor(); };`
281			`EOR_ZPX: { exec_eor(); };`
282			`EOR_ABS: { exec_eor(); };`
283			`EOR_ABX: { exec_eor(); };`
284			`EOR_ABY: { exec_eor(); };`
285			`EOR_IDX: { exec_eor(); };`
286			`EOR_IDY: { exec_eor(); };`
287
288			`INC_ZPG: { exec_inc(inst.alu_a, TRUE); };`
289			`INC_ZPX: { exec_inc(inst.alu_a, TRUE); };`
290			`INC_ABS: { exec_inc(inst.alu_a, TRUE); };`
291			`INC_ABX: { exec_inc(inst.alu_a, TRUE); };`
292
293			`INX_IMP: { exec_inc(reg_x, FALSE); };`
294			`INY_IMP: { exec_inc(reg_y, FALSE); };`
295
296			`JMP_ABS: {};`
297			`JMP_IND: {};`
298			`JSR_ABS: {};`
299
300			`LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M`
301			`LDA_ZPG: { exec_load(reg_a, TRUE); };`
302			`LDA_ZPX: { exec_load(reg_a, TRUE); };`
303			`LDA_ABS: { exec_load(reg_a, TRUE); };`
304			`LDA_ABX: { exec_load(reg_a, TRUE); };`
305			`LDA_ABY: { exec_load(reg_a, TRUE); };`
306			`LDA_IDX: { exec_load(reg_a, TRUE); };`
307			`LDA_IDY: { exec_load(reg_a, TRUE); };`
308
309			`LDX_IMM: { exec_load(reg_x, FALSE); };`
310			`LDX_ZPG: { exec_load(reg_x, FALSE); };`
311			`LDX_ZPY: { exec_load(reg_x, FALSE); };`
312			`LDX_ABS: { exec_load(reg_x, FALSE); };`
313			`LDX_ABY: { exec_load(reg_x, FALSE); };`
314
315			`LDY_IMM: { exec_load(reg_y, FALSE); };`
316			`LDY_ZPG: { exec_load(reg_y, FALSE); };`
317			`LDY_ZPX: { exec_load(reg_y, FALSE); };`
318			`LDY_ABS: { exec_load(reg_y, FALSE); };`
319			`LDY_ABX: { exec_load(reg_y, FALSE); };`
320
321			`LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2`
322			`LSR_ZPG: { exec_lsr(inst.alu_a); };`
323			`LSR_ZPX: { exec_lsr(inst.alu_a); };`
324			`LSR_ABS: { exec_lsr(inst.alu_a); };`
325			`LSR_ABX: { exec_lsr(inst.alu_a); };`
326
327			`NOP_IMP: {};`
328
329			`ORA_IMM: { exec_or(); }; // A,Z,N = A\|M`
330			`ORA_ZPG: { exec_or(); };`
331			`ORA_ZPX: { exec_or(); };`
332			`ORA_ABS: { exec_or(); };`
333			`ORA_ABX: { exec_or(); };`
334			`ORA_ABY: { exec_or(); };`
335			`ORA_IDX: { exec_or(); };`
336			`ORA_IDY: { exec_or(); };`
337
338			`PHA_IMP: { reg_result = reg_a; };`
339			`PHP_IMP: {}; // P is always connected and the result is not updated`
340			`PLA_IMP: {`
341			`reg_a = inst.alu_a;`
342			`reg_result = inst.alu_a;`
343			`update_z(reg_a);`
344			`update_n(reg_a);`
345			`};`
346			`PLP_IMP: {`
347			`reg_status = inst.alu_a;`
348			`reg_status[5:5] = 1; // this is always one`
349			`};`
350
351	185	creep	`ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };`
352	177	creep	`ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };`
353			`ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };`
354			`ROL_ABS: { exec_rot(TRUE, inst.alu_a); };`
355			`ROL_ABX: { exec_rot(TRUE, inst.alu_a); };`
356	185	creep	`ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };`
357	177	creep	`ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };`
358			`ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };`
359			`ROR_ABS: { exec_rot(FALSE, inst.alu_a); };`
360			`ROR_ABX: { exec_rot(FALSE, inst.alu_a); };`
361	160	creep
362	177	creep	`RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };`
363			`RTS_IMP: { };`
364
365			`SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)`
366			`SBC_ZPG: { exec_sub(); };`
367			`SBC_ZPX: { exec_sub(); };`
368			`SBC_ABS: { exec_sub(); };`
369			`SBC_ABX: { exec_sub(); };`
370			`SBC_ABY: { exec_sub(); };`
371			`SBC_IDX: { exec_sub(); };`
372			`SBC_IDY: { exec_sub(); };`
373
374			`SEC_IMP: { reg_status[0:0] = 1; };`
375			`SED_IMP: { reg_status[3:3] = 1; };`
376			`SEI_IMP: { reg_status[2:2] = 1; };`
377
378			`STA_ZPG: { reg_result = reg_a; };`
379			`STA_ZPX: { reg_result = reg_a; };`
380			`STA_ABS: { reg_result = reg_a; };`
381			`STA_ABX: { reg_result = reg_a; };`
382			`STA_ABY: { reg_result = reg_a; };`
383			`STA_IDX: { reg_result = reg_a; };`
384			`STA_IDY: { reg_result = reg_a; };`
385	182	creep	`STX_ZPG: { };`
386			`STX_ZPY: { };`
387			`STX_ABS: { };`
388			`STY_ZPG: { };`
389			`STY_ZPX: { };`
390			`STY_ABS: { };`
391	177	creep
392	182	creep	`TAX_IMP: { exec_transfer(reg_a, reg_x); };`
393			`TAY_IMP: { exec_transfer(reg_a, reg_y); };`
394			`TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };`
395			`TXA_IMP: { exec_transfer(reg_x, reg_a); };`
396			`TXS_IMP: { };`
397	185	creep	`TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y`
398	177	creep
399	185	creep	`// note: tya and txa do not update the result register`
400
401	132	creep	`default: {`
402	182	creep	`// all the random generated opcodes will fall here`
403	132	creep	`}`
404			`};`
405			`};`
406
407	177	creep	`exec_transfer(source : byte, dest : *byte) is {`
408			`dest = source;`
409			`update_z(dest);`
410			`update_n(dest);`
411			`};`
412
413			`exec_sub() is {`
414			`if (reg_status[3:3] == 1) {`
415			`var op1 : int;`
416			`var op2 : int;`
417
418	185	creep	`warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");`
419
420	177	creep	`//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);`
421
422			`op1 = inst.alu_a[3:0];`
423			`op2 = inst.alu_a[7:4];`
424
425			`op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];`
426			`op2 = reg_a[7:4] - op2;`
427
428			`if (op1 >= 10) {`
429			`op2 = op2 + op1/10;`
430			`op1 = op1 % 10;`
431			`} else if (op1 < 0) {`
432			`op2 = op2 - op1/10;`
433			`op1 = -(op1 % 10);`
434			`};`
435
436	182	creep	`reg_status[0:0] = 1;`
437
438	177	creep	`if (op2 >= 10) {`
439			`op2 = op2 % 10;`
440			`}`
441			`else if (op2 < 0) {`
442			`op2 = op2 + 10;`
443			`reg_status[0:0] = 0;`
444			`};`
445
446			`reg_result[3:0] = op1;`
447	185	creep	`reg_result[7:4] = op2;`
448	177	creep	`}`
449			`else {`
450			`reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];`
451			`if (reg_result[7:7] == 1) {`
452			`reg_status[0:0] = 0;`
453			`}`
454			`else {`
455			`reg_status[0:0] = 1;`
456			`};`
457			`};`
458
459			`update_z(reg_result);`
460			`update_n(reg_result);`
461			`update_v(reg_a, inst.alu_a, reg_result);`
462
463
464			`reg_a = reg_result;`
465
466			`};`
467
468	185	creep	`exec_rot(left : bool, arg1 : byte) is {`
469	160	creep	`var oldcarry : bit;`
470
471	177	creep	`if (left) {`
472			`oldcarry = reg_status[0:0];`
473			`reg_status[0:0] = arg1[7:7];`
474	185	creep	`reg_result = arg1 << 1;`
475			`reg_result[0:0] = oldcarry;`
476	177	creep	`}`
477			`else {`
478			`oldcarry = reg_status[0:0];`
479			`reg_status[0:0] = arg1[0:0];`
480	185	creep	`reg_result = arg1 >> 1;`
481			`reg_result[7:7] = oldcarry;`
482	177	creep	`};`
483	160	creep
484	185	creep	`update_z(reg_result);`
485			`update_n(reg_result);`
486	160	creep	`};`
487
488	159	creep	`exec_or() is {`
489			`reg_a = reg_a \| inst.alu_a;`
490			`reg_result = reg_a;`
491			`update_z(reg_a);`
492			`update_n(reg_a);`
493			`};`
494
495			`exec_lsr(arg1 : *byte) is {`
496			`reg_status[0:0] = arg1[0:0];`
497			`arg1 = arg1 >> 1;`
498			`update_z(arg1);`
499			`update_n(arg1);`
500			`reg_result = arg1;`

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