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[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Blame information for rev 235

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1 131 creep
alu_chk.e
2
<'
3
import alu_components;
4
 
5
unit alu_chk_u {
6
        reg_a : byte;
7
        reg_x : byte;
8
        reg_y : byte;
9
        reg_status : byte;
10 135 creep
        reg_result : byte;
11 131 creep
 
12 159 creep
        !inst : alu_input_s;
13
        !next_inst : alu_input_s;
14 132 creep
 
15 131 creep
        count_cycles : int;
16
        first_cycle : bool;
17 159 creep
        last_a : byte;
18
        last_status : byte;
19
        last_result : byte;
20 182 creep
        rst_counter : byte;
21 131 creep
 
22
        keep first_cycle == TRUE;
23
        keep count_cycles == 0;
24 182 creep
        keep rst_counter == 0;
25 131 creep
 
26 182 creep
        event T3_cover_event;
27
        cover T3_cover_event is {
28
                item rst_counter; // using num_of_buckets=100;
29
        };
30
 
31
 
32 131 creep
        store(input : alu_input_s) is {
33 134 creep
                count_cycles = count_cycles + 1;
34
 
35 153 creep
                //out ("CYCLE ", count_cycles, " STORE:");
36
                //print input;
37 132 creep
 
38 159 creep
                last_a = reg_a;
39
                last_status = reg_status;
40
                last_result = reg_result;
41
 
42 132 creep
                if (first_cycle) {
43
                        inst = input;
44
                        next_inst = input;
45
                }
46
                else {
47
                        inst = next_inst;
48
                        next_inst = input;
49
                };
50
 
51 131 creep
        };
52
 
53
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
54
                if (first_cycle) {
55
                        first_cycle = FALSE;
56 143 creep
                        reg_x = 0;
57
                        reg_y = 0;
58
                        reg_status = 8'b00100010;
59 185 creep
                        reg_a = 0;
60 135 creep
                        reg_result = 0;
61 131 creep
                }
62 132 creep
                else {
63 185 creep
                        //out ("CYCLE ", count_cycles, " COMPARE:");
64
                        //print inst;
65 134 creep
 
66 159 creep
                        if (count_cycles == 99999) {
67
                                out("ENOUGH!");
68
                                stop_run();
69
                        };
70
 
71 182 creep
                        if (inst.input_kind == RESET) {
72
                                rst_counter = rst_counter + 1;
73
                        }
74
                        else {
75
                                emit T3_cover_event;
76
                                rst_counter = 0;
77
                        };
78
 
79 132 creep
                        case inst.input_kind {
80
                                ENABLED_VALID: {
81 153 creep
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
82 185 creep
                                        execute(inst.alu_opcode);
83 132 creep
                                };
84 143 creep
                                RESET: {
85 146 creep
                                        reg_x = 0;
86
                                        reg_y = 0;
87
                                        reg_status = 8'b00100010;
88 235 creep
                                        reg_a = 0;
89 146 creep
                                        reg_result = 0;
90
 
91 143 creep
                                        return;
92
                                };
93 182 creep
                                ENABLED_RAND: {
94 185 creep
                                        execute(inst.rand_op.as_a(valid_opcodes));
95
 
96
                                        if (reg_status[3:3] == 1) {
97
                                                case inst.rand_op.as_a(valid_opcodes) {
98
                                                        SBC_IMM: {
99
                                                                reg_a = alu_result;
100
                                                                reg_result = alu_result;
101
                                                                reg_status = alu_status;
102
                                                        };
103
                                                        SBC_ZPG: {
104
                                                                reg_a = alu_result;
105
                                                                reg_result = alu_result;
106
                                                                reg_status = alu_status;
107
                                                        };
108
                                                        SBC_ZPX: {
109
                                                                reg_a = alu_result;
110
                                                                reg_result = alu_result;
111
                                                                reg_status = alu_status;
112
                                                        };
113
                                                        SBC_ABS: {
114
                                                                reg_a = alu_result;
115
                                                                reg_result = alu_result;
116
                                                                reg_status = alu_status;
117
                                                        };
118
                                                        SBC_ABX: {
119
                                                                reg_a = alu_result;
120
                                                                reg_result = alu_result;
121
                                                                reg_status = alu_status;
122
                                                        };
123
                                                        SBC_ABY: {
124
                                                                reg_a = alu_result;
125
                                                                reg_result = alu_result;
126
                                                                reg_status = alu_status;
127
                                                        };
128
                                                        SBC_IDX: {
129
                                                                reg_a = alu_result;
130
                                                                reg_result = alu_result;
131
                                                                reg_status = alu_status;
132
                                                        };
133
                                                        SBC_IDY: {
134
                                                                reg_a = alu_result;
135
                                                                reg_result = alu_result;
136
                                                                reg_status = alu_status;
137
                                                        };
138
                                                };
139
                                        };
140
 
141 182 creep
                                };
142 132 creep
                                default: {
143
                                };
144
                        };
145
 
146 133 creep
                        // here i have already calculated. must compare!
147 143 creep
 
148 146 creep
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
149 153 creep
                                out("#########################################################");
150 135 creep
                                print me;
151 155 creep
                                print me.inst;
152 153 creep
                                out("#########################################################");
153 134 creep
                                print alu_result;
154 135 creep
                                print alu_status;
155
                                print alu_x;
156
                                print alu_y;
157
 
158 133 creep
                                dut_error("WRONG!");
159
                        };
160 146 creep
                };
161 131 creep
        };
162 132 creep
 
163 185 creep
        execute(opcode : valid_opcodes) is {
164
                case opcode {
165 132 creep
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
166
                        ADC_ZPG: { exec_sum(); };
167
                        ADC_ZPX: { exec_sum(); };
168
                        ADC_ABS: { exec_sum(); };
169
                        ADC_ABX: { exec_sum(); };
170
                        ADC_ABY: { exec_sum(); };
171
                        ADC_IDX: { exec_sum(); };
172
                        ADC_IDY: { exec_sum(); };
173
 
174 133 creep
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
175 132 creep
                        AND_ZPG: { exec_and(); };
176
                        AND_ZPX: { exec_and(); };
177
                        AND_ABS: { exec_and(); };
178
                        AND_ABX: { exec_and(); };
179
                        AND_ABY: { exec_and(); };
180
                        AND_IDX: { exec_and(); };
181
                        AND_IDY: { exec_and(); };
182
 
183 135 creep
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
184 132 creep
 
185 135 creep
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
186
                        ASL_ZPX: { exec_asl_mem(); };
187
                        ASL_ABS: { exec_asl_mem(); };
188
                        ASL_ABX: { exec_asl_mem(); };
189
 
190 155 creep
                        BCC_REL: {}; // nothing is done. these are all branches.
191 153 creep
                        BCS_REL: {};
192
                        BEQ_REL: {};
193 155 creep
                        BMI_REL: {};
194
                        BNE_REL: {};
195
                        BPL_REL: {};
196
                        BVC_REL: {};
197
                        BVS_REL: {};
198 153 creep
 
199 155 creep
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
200
                        BIT_ABS: { exec_bit(); };
201
 
202
                        BRK_IMP: { reg_status[4:4] = 1; };
203
 
204
                        CLC_IMP: { reg_status[0:0] = 0; };
205
                        CLD_IMP: { reg_status[3:3] = 0; };
206
                        CLI_IMP: { reg_status[2:2] = 0; };
207
                        CLV_IMP: { reg_status[6:6] = 0; };
208
 
209 159 creep
                        CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
210
                        CMP_ZPG: { exec_cmp(reg_a); };
211
                        CMP_ZPX: { exec_cmp(reg_a); };
212
                        CMP_ABS: { exec_cmp(reg_a); };
213
                        CMP_ABX: { exec_cmp(reg_a); };
214
                        CMP_ABY: { exec_cmp(reg_a); };
215
                        CMP_IDX: { exec_cmp(reg_a); };
216
                        CMP_IDY: { exec_cmp(reg_a); };
217
 
218
                        CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
219
                        CPX_ZPG: { exec_cmp(reg_x); };
220
                        CPX_ABS: { exec_cmp(reg_x); };
221
 
222
                        CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
223
                        CPY_ZPG: { exec_cmp(reg_y); };
224
                        CPY_ABS: { exec_cmp(reg_y); };
225
 
226
                        DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
227
                        DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
228
                        DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
229
                        DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
230
 
231
                        DEX_IMP: { exec_dec(reg_x, FALSE); };  // X,Z,N = X-1
232
                        DEY_IMP: { exec_dec(reg_y, FALSE); };  // Y,Z,N = Y-1
233
 
234
                        EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
235
                        EOR_ZPG: { exec_eor(); };
236
                        EOR_ZPX: { exec_eor(); };
237
                        EOR_ABS: { exec_eor(); };
238
                        EOR_ABX: { exec_eor(); };
239
                        EOR_ABY: { exec_eor(); };
240
                        EOR_IDX: { exec_eor(); };
241
                        EOR_IDY: { exec_eor(); };
242
 
243
                        INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
244
                        INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
245
                        INC_ABS: { exec_inc(inst.alu_a, TRUE); };
246
                        INC_ABX: { exec_inc(inst.alu_a, TRUE); };
247
 
248
                        INX_IMP: { exec_inc(reg_x, FALSE); };
249
                        INY_IMP: { exec_inc(reg_y, FALSE); };
250
 
251
                        JMP_ABS: {};
252
                        JMP_IND: {};
253
                        JSR_ABS: {};
254
 
255
                        LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
256
                        LDA_ZPG: { exec_load(reg_a, TRUE); };
257
                        LDA_ZPX: { exec_load(reg_a, TRUE); };
258
                        LDA_ABS: { exec_load(reg_a, TRUE); };
259
                        LDA_ABX: { exec_load(reg_a, TRUE); };
260
                        LDA_ABY: { exec_load(reg_a, TRUE); };
261
                        LDA_IDX: { exec_load(reg_a, TRUE); };
262
                        LDA_IDY: { exec_load(reg_a, TRUE); };
263
 
264
                        LDX_IMM: { exec_load(reg_x, FALSE); };
265
                        LDX_ZPG: { exec_load(reg_x, FALSE); };
266
                        LDX_ZPY: { exec_load(reg_x, FALSE); };
267
                        LDX_ABS: { exec_load(reg_x, FALSE); };
268
                        LDX_ABY: { exec_load(reg_x, FALSE); };
269
 
270
                        LDY_IMM: { exec_load(reg_y, FALSE); };
271
                        LDY_ZPG: { exec_load(reg_y, FALSE); };
272
                        LDY_ZPX: { exec_load(reg_y, FALSE); };
273
                        LDY_ABS: { exec_load(reg_y, FALSE); };
274
                        LDY_ABX: { exec_load(reg_y, FALSE); };
275
 
276
                        LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
277
                        LSR_ZPG: { exec_lsr(inst.alu_a); };
278
                        LSR_ZPX: { exec_lsr(inst.alu_a); };
279
                        LSR_ABS: { exec_lsr(inst.alu_a); };
280
                        LSR_ABX: { exec_lsr(inst.alu_a); };
281
 
282
                        NOP_IMP: {};
283
 
284
                        ORA_IMM: { exec_or(); }; // A,Z,N = A|M
285
                        ORA_ZPG: { exec_or(); };
286
                        ORA_ZPX: { exec_or(); };
287
                        ORA_ABS: { exec_or(); };
288
                        ORA_ABX: { exec_or(); };
289
                        ORA_ABY: { exec_or(); };
290
                        ORA_IDX: { exec_or(); };
291
                        ORA_IDY: { exec_or(); };
292
 
293
                        PHA_IMP: { reg_result = reg_a; };
294
                        PHP_IMP: {}; // P is always connected and the result is not updated
295
                        PLA_IMP: {
296
                                reg_a = inst.alu_a;
297
                                reg_result = inst.alu_a;
298
                                update_z(reg_a);
299
                                update_n(reg_a);
300
                        };
301
                        PLP_IMP: {
302
                                reg_status = inst.alu_a;
303
                                reg_status[5:5] = 1; // this is always one
304
                        };
305
 
306 185 creep
                        ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
307 177 creep
                        ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
308
                        ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
309
                        ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
310
                        ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
311 185 creep
                        ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
312 177 creep
                        ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
313
                        ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
314
                        ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
315
                        ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
316 160 creep
 
317 177 creep
                        RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
318
                        RTS_IMP: { };
319
 
320
                        SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
321
                        SBC_ZPG: { exec_sub(); };
322
                        SBC_ZPX: { exec_sub(); };
323
                        SBC_ABS: { exec_sub(); };
324
                        SBC_ABX: { exec_sub(); };
325
                        SBC_ABY: { exec_sub(); };
326
                        SBC_IDX: { exec_sub(); };
327
                        SBC_IDY: { exec_sub(); };
328
 
329
                        SEC_IMP: { reg_status[0:0] = 1; };
330
                        SED_IMP: { reg_status[3:3] = 1; };
331
                        SEI_IMP: { reg_status[2:2] = 1; };
332
 
333
                        STA_ZPG: { reg_result = reg_a; };
334
                        STA_ZPX: { reg_result = reg_a; };
335
                        STA_ABS: { reg_result = reg_a; };
336
                        STA_ABX: { reg_result = reg_a; };
337
                        STA_ABY: { reg_result = reg_a; };
338
                        STA_IDX: { reg_result = reg_a; };
339
                        STA_IDY: { reg_result = reg_a; };
340 182 creep
                        STX_ZPG: { };
341
                        STX_ZPY: { };
342
                        STX_ABS: { };
343
                        STY_ZPG: { };
344
                        STY_ZPX: { };
345
                        STY_ABS: { };
346 177 creep
 
347 182 creep
                        TAX_IMP: { exec_transfer(reg_a, reg_x); };
348
                        TAY_IMP: { exec_transfer(reg_a, reg_y); };
349
                        TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
350
                        TXA_IMP: { exec_transfer(reg_x, reg_a); };
351
                        TXS_IMP: { };
352 185 creep
                        TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
353 177 creep
 
354 185 creep
                        // note: tya and txa do not update the result register
355
 
356 132 creep
                        default: {
357 182 creep
                                // all the random generated opcodes will fall here
358 132 creep
                        }
359
                };
360
        };
361
 
362 177 creep
        exec_transfer(source : byte, dest : *byte) is {
363
                dest = source;
364
                update_z(dest);
365
                update_n(dest);
366
        };
367
 
368
        exec_sub() is {
369 235 creep
                var temp: int;
370
 
371
                temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
372
                reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
373
 
374
                reg_status[7:7] = temp[7:7]; // N
375
                //print  (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
376
                reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
377
 
378
                print reg_result;
379
                if (reg_result == 0) {
380
                        reg_status[1:1] = 1; // Z
381
                } else {
382
                        reg_status[1:1] = 0; // Z
383
                };
384
 
385 233 creep
                if (reg_status[3:3] == 1) { // decimal
386 177 creep
                        var op1 : int;
387
                        var op2 : int;
388
 
389 235 creep
                        op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);
390
                        print op1;
391
                        op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);
392
                        print op2;
393 185 creep
 
394 235 creep
                        if (op1[4:4] == 1) {
395
                                op1 -= 6;
396
                                op2 = op2 - 1;
397 177 creep
                        };
398 235 creep
                        print op1;
399
                        print op2;
400
 
401
                        if(op2[8:8] == 1) {
402
                              op2 -= 0x60;
403
                        };
404
                        print op2;
405 177 creep
 
406 235 creep
                        reg_a = (op1 & 0x0f) | (op2 & 0xf0);
407
                        reg_result = reg_a;
408 177 creep
                }
409
                else {
410 233 creep
                        reg_a = temp.as_a(byte);
411 177 creep
                };
412 235 creep
 
413
                if ( (temp & 0xff00) != 0x0000 ) {
414
                        reg_status[0:0] = 0;
415
                } else {
416
                        reg_status[0:0] = 1;
417
                };
418 177 creep
        };
419
 
420 185 creep
        exec_rot(left : bool, arg1 : byte) is {
421 160 creep
                var oldcarry : bit;
422
 
423 177 creep
                if (left) {
424
                        oldcarry = reg_status[0:0];
425
                        reg_status[0:0] = arg1[7:7];
426 185 creep
                        reg_result = arg1 << 1;
427
                        reg_result[0:0] = oldcarry;
428 177 creep
                }
429
                else {
430
                        oldcarry = reg_status[0:0];
431
                        reg_status[0:0] = arg1[0:0];
432 185 creep
                        reg_result = arg1 >> 1;
433
                        reg_result[7:7] = oldcarry;
434 177 creep
                };
435 160 creep
 
436 185 creep
                update_z(reg_result);
437
                update_n(reg_result);
438 160 creep
        };
439
 
440 159 creep
        exec_or() is {
441
                reg_a = reg_a | inst.alu_a;
442
                reg_result = reg_a;
443
                update_z(reg_a);
444
                update_n(reg_a);
445
        };
446
 
447
        exec_lsr(arg1 : *byte) is {
448
                reg_status[0:0] = arg1[0:0];
449
                arg1 = arg1 >> 1;
450
                update_z(arg1);
451
                update_n(arg1);
452
                reg_result = arg1;
453
        };
454
 
455
        exec_load(arg1 : *byte, update_result : bool) is {
456
                arg1 = inst.alu_a;
457
 
458
                if (update_result) { //
459
                        reg_result = inst.alu_a; // no need for this but...
460
                };
461
                update_z(arg1);
462
                update_n(arg1);
463
        };
464
 
465
        exec_inc(arg1 : *byte, update_result : bool) is {
466
                arg1 = arg1 + 1;
467
                update_z(arg1);
468
                update_n(arg1);
469
 
470
                if (update_result) { //
471
                        reg_result = arg1;
472
                };
473
        };
474
 
475
        exec_eor() is {
476
                reg_a = reg_a ^ inst.alu_a;
477
                reg_result = reg_a;
478
                update_z(reg_a);
479
                update_n(reg_a);
480
        };
481
 
482
        exec_dec(arg1 : *byte, update_result : bool) is {
483
                arg1 = arg1 - 1;
484
                update_z(arg1);
485
                update_n(arg1);
486
 
487
                if (update_result) { // DEX and DEY do not output the result
488
                        reg_result = arg1;
489
                };
490
        };
491
 
492
        exec_cmp(arg1 : byte) is {
493
                update_z(arg1 - inst.alu_a);
494
                update_n(arg1 - inst.alu_a);
495
 
496
                if (arg1 >= inst.alu_a) {
497
                        reg_status[0:0] = 1;
498
                }
499
                else {
500
                        reg_status[0:0] = 0;
501
                };
502
        };
503
 
504 155 creep
        exec_bit() is {
505
                update_z(reg_a & inst.alu_a);
506
                reg_status[7:7] = inst.alu_a[7:7];
507
                reg_status[6:6] = inst.alu_a[6:6];
508
        };
509
 
510 135 creep
        exec_asl_acc() is {
511
                reg_status[0:0] = reg_a[7:7];
512
                reg_a = reg_a * 2;
513
                update_z(reg_a);
514
                update_n(reg_a);
515
                reg_result = reg_a;
516
        };
517
 
518
        exec_asl_mem() is {
519
                reg_status[0:0] = inst.alu_a[7:7];
520
                reg_result = inst.alu_a * 2;
521
                update_z(reg_result);
522
                update_n(reg_result);
523
        };
524
 
525 132 creep
        exec_and() is {
526 133 creep
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
527
                update_z(reg_a);
528
                update_n(reg_a);
529 135 creep
                reg_result = reg_a;
530 132 creep
        };
531
 
532
        exec_sum() is {
533 153 creep
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
534 160 creep
                if (reg_status[3:3] == 1) {
535
                        var op1 : byte;
536
                        var op2 : byte;
537 234 creep
                        var aux : byte;
538 160 creep
 
539 234 creep
                        op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
540
                        //Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
541 160 creep
 
542 234 creep
                        op2 = reg_a[7:4] + inst.alu_a[7:4];
543
                        //carry_aux = reg_a[7:4] + inst.alu_a[7:4];
544
                        //Int32 hi = (A & 0xf0) + (operand & 0xf0);
545
 
546
                        aux = op1 + op2;
547
 
548
                        if (aux[7:0] == 0) {
549
                                reg_status[1:1] = 1;
550 160 creep
                        }
551
                        else {
552 234 creep
                                reg_status[1:1] = 0;
553 160 creep
                        };
554 234 creep
                        //notZ = (lo+hi) & 0xff;
555
 
556
                        if (op1 > 0x09) {
557
                                op2 += 0x01;
558
                                op1 += 0x06;
559
                        };
560
 
561
                        reg_status[7:7] = op2[3:3];
562
                        //N = hi & 0x80;
563
 
564
                        reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
565
                        //V = ~(A ^ operand) & (A ^ hi) & 0x80;
566
                        if (op2 > 0x09) {
567
                                op2 += 0x06;
568
                        };
569
                        //if (hi > 0x90) hi += 0x60;
570
 
571
                        reg_status[0:0] = (op2 > 15) ? 1 : 0;
572
                        //C = hi & 0xff00;
573
 
574
                        reg_a[3:0] = op1[3:0];
575
                        reg_a[7:4] = op2[3:0];
576
                        //reg_a = (lo & 0x0f) + (hi & 0xf0);
577 160 creep
 
578 234 creep
                        reg_result = reg_a;
579 160 creep
                }
580 233 creep
                else { // stella checked
581 160 creep
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
582 233 creep
                        update_n(reg_result);
583 160 creep
                        update_v(reg_a, inst.alu_a, reg_result);
584
                        update_z(reg_result);
585 233 creep
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
586
 
587 160 creep
                        reg_a = reg_result;
588
                };
589 132 creep
        };
590
 
591 143 creep
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
592 153 creep
                if (arg1 + arg2 + arg3 > 255) {
593 132 creep
                        reg_status[0:0] = 1;
594
                }
595
                else {
596
                        reg_status[0:0] = 0;
597
                }
598
        };
599
 
600 146 creep
        update_v(op1 : byte, op2 : byte, res : byte) is {
601
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
602
                        reg_status[6:6] = 1;
603
                }
604
                else {
605
                        reg_status[6:6] = 0;
606
                };
607
        };
608
 
609
        update_z(arg : byte) is {
610
                if (arg == 0) {
611
                        reg_status[1:1] = 1;
612
                }
613
                else {
614
                        reg_status[1:1] = 0;
615
                }
616
        };
617
 
618
 
619 132 creep
        update_n(arg : byte) is {
620
                if (arg[7:7] == 1) {
621
                        reg_status[7:7] = 1;
622
                }
623
                else {
624
                        reg_status[7:7] = 0;
625
                }
626
        };
627 131 creep
};
628
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