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alu_chk.e
<'
import alu_components;
 
unit alu_chk_u {
        reg_a : byte;
        reg_x : byte;
        reg_y : byte;
        reg_status : byte;
        reg_result : byte;
 
        !inst : alu_input_s;
        !next_inst : alu_input_s;
 
        count_cycles : int;
        first_cycle : bool;
        last_a : byte;
        last_status : byte;
        last_result : byte;
        rst_counter : byte;
 
        keep first_cycle == TRUE;
        keep count_cycles == 0;
        keep rst_counter == 0;
 
        event T3_cover_event;
        cover T3_cover_event is {
                item rst_counter; // using num_of_buckets=100;
        };
 
 
        store(input : alu_input_s) is {
                count_cycles = count_cycles + 1;
 
                //out ("CYCLE ", count_cycles, " STORE:");
                //print input;
 
                last_a = reg_a;
                last_status = reg_status;
                last_result = reg_result;
 
                if (first_cycle) {
                        inst = input;
                        next_inst = input;
                }
                else {
                        inst = next_inst;
                        next_inst = input;
                };
 
        };
 
        compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
                if (first_cycle) {
                        first_cycle = FALSE;
                        reg_x = 0;
                        reg_y = 0;
                        reg_status = 8'b00100010;
                        reg_a = 0;
                        reg_result = 0;
                }
                else {
                        //out ("CYCLE ", count_cycles, " COMPARE:");
                        //print inst;
 
                        if (count_cycles == 99999) {
                                out("ENOUGH!");
                                stop_run();
                        };
 
                        if (inst.input_kind == RESET) {
                                rst_counter = rst_counter + 1;
                        }
                        else {
                                emit T3_cover_event;
                                rst_counter = 0;
                        };
 
                        case inst.input_kind {
                                ENABLED_VALID: {
                                        //out("CYCLE ", count_cycles, ": executing and comparing");
                                        execute(inst.alu_opcode);
                                };
                                RESET: {
                                        reg_x = 0;
                                        reg_y = 0;
                                        reg_status = 8'b00100010;
                                        reg_a = 0;
                                        reg_result = 0;
 
                                        return;
                                };
                                ENABLED_RAND: {
                                        execute(inst.rand_op.as_a(valid_opcodes));
 
                                        if (reg_status[3:3] == 1) {
                                                case inst.rand_op.as_a(valid_opcodes) {
                                                        SBC_IMM: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPG: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ZPX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABS: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_ABY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDX: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                        SBC_IDY: {
                                                                reg_a = alu_result;
                                                                reg_result = alu_result;
                                                                reg_status = alu_status;
                                                        };
                                                };
                                        };
 
                                };
                                default: {
                                };
                        };
 
                        // here i have already calculated. must compare!
 
                        if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
                                out("#########################################################");
                                print me;
                                print me.inst;
                                out("#########################################################");
                                print alu_result;
                                print alu_status;
                                print alu_x;
                                print alu_y;
 
                                dut_error("WRONG!");
                        };
                };
        };
 
        execute(opcode : valid_opcodes) is {
                case opcode {
                        ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
                        ADC_ZPG: { exec_sum(); };
                        ADC_ZPX: { exec_sum(); };
                        ADC_ABS: { exec_sum(); };
                        ADC_ABX: { exec_sum(); };
                        ADC_ABY: { exec_sum(); };
                        ADC_IDX: { exec_sum(); };
                        ADC_IDY: { exec_sum(); };
 
                        AND_IMM: { exec_and(); }; // A,Z,N = A&M
                        AND_ZPG: { exec_and(); };
                        AND_ZPX: { exec_and(); };
                        AND_ABS: { exec_and(); };
                        AND_ABX: { exec_and(); };
                        AND_ABY: { exec_and(); };
                        AND_IDX: { exec_and(); };
                        AND_IDY: { exec_and(); };
 
                        ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
 
                        ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
                        ASL_ZPX: { exec_asl_mem(); };
                        ASL_ABS: { exec_asl_mem(); };
                        ASL_ABX: { exec_asl_mem(); };
 
                        //BCC_REL: {}; // nothing is done. these are all branches.
                        //BCS_REL: {};
                        //BEQ_REL: {};
                        //BMI_REL: {};
                        //BNE_REL: {};
                        //BPL_REL: {};
                        //BVC_REL: {};
                        //BVS_REL: {};
 
                        BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
                        BIT_ABS: { exec_bit(); };
 
                        BRK_IMP: { reg_status[4:4] = 1; };
 
                        CLC_IMP: { reg_status[0:0] = 0; };
                        CLD_IMP: { reg_status[3:3] = 0; };
                        CLI_IMP: { reg_status[2:2] = 0; };
                        CLV_IMP: { reg_status[6:6] = 0; };
 
                        CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
                        CMP_ZPG: { exec_cmp(reg_a); };
                        CMP_ZPX: { exec_cmp(reg_a); };
                        CMP_ABS: { exec_cmp(reg_a); };
                        CMP_ABX: { exec_cmp(reg_a); };
                        CMP_ABY: { exec_cmp(reg_a); };
                        CMP_IDX: { exec_cmp(reg_a); };
                        CMP_IDY: { exec_cmp(reg_a); };
 
                        CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
                        CPX_ZPG: { exec_cmp(reg_x); };
                        CPX_ABS: { exec_cmp(reg_x); };
 
                        CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
                        CPY_ZPG: { exec_cmp(reg_y); };
                        CPY_ABS: { exec_cmp(reg_y); };
 
                        DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
                        DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
                        DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
 
                        DEX_IMP: { exec_dec(reg_x, FALSE); };  // X,Z,N = X-1
                        DEY_IMP: { exec_dec(reg_y, FALSE); };  // Y,Z,N = Y-1
 
                        EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
                        EOR_ZPG: { exec_eor(); };
                        EOR_ZPX: { exec_eor(); };
                        EOR_ABS: { exec_eor(); };
                        EOR_ABX: { exec_eor(); };
                        EOR_ABY: { exec_eor(); };
                        EOR_IDX: { exec_eor(); };
                        EOR_IDY: { exec_eor(); };
 
                        INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
                        INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABS: { exec_inc(inst.alu_a, TRUE); };
                        INC_ABX: { exec_inc(inst.alu_a, TRUE); };
 
                        INX_IMP: { exec_inc(reg_x, FALSE); };
                        INY_IMP: { exec_inc(reg_y, FALSE); };
 
                        //JMP_ABS: {};
                        //JMP_IND: {};
                        //JSR_ABS: {};
 
                        LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
                        LDA_ZPG: { exec_load(reg_a, TRUE); };
                        LDA_ZPX: { exec_load(reg_a, TRUE); };
                        LDA_ABS: { exec_load(reg_a, TRUE); };
                        LDA_ABX: { exec_load(reg_a, TRUE); };
                        LDA_ABY: { exec_load(reg_a, TRUE); };
                        LDA_IDX: { exec_load(reg_a, TRUE); };
                        LDA_IDY: { exec_load(reg_a, TRUE); };
 
                        LDX_IMM: { exec_load(reg_x, FALSE); };
                        LDX_ZPG: { exec_load(reg_x, FALSE); };
                        LDX_ZPY: { exec_load(reg_x, FALSE); };
                        LDX_ABS: { exec_load(reg_x, FALSE); };
                        LDX_ABY: { exec_load(reg_x, FALSE); };
 
                        LDY_IMM: { exec_load(reg_y, FALSE); };
                        LDY_ZPG: { exec_load(reg_y, FALSE); };
                        LDY_ZPX: { exec_load(reg_y, FALSE); };
                        LDY_ABS: { exec_load(reg_y, FALSE); };
                        LDY_ABX: { exec_load(reg_y, FALSE); };
 
                        LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
                        LSR_ZPG: { exec_lsr(inst.alu_a); };
                        LSR_ZPX: { exec_lsr(inst.alu_a); };
                        LSR_ABS: { exec_lsr(inst.alu_a); };
                        LSR_ABX: { exec_lsr(inst.alu_a); };
 
                        //NOP_IMP: {};
 
                        ORA_IMM: { exec_or(); }; // A,Z,N = A|M
                        ORA_ZPG: { exec_or(); };
                        ORA_ZPX: { exec_or(); };
                        ORA_ABS: { exec_or(); };
                        ORA_ABX: { exec_or(); };
                        ORA_ABY: { exec_or(); };
                        ORA_IDX: { exec_or(); };
                        ORA_IDY: { exec_or(); };
 
                        PHA_IMP: { reg_result = reg_a; };
                        //PHP_IMP: {}; // P is always connected and the result is not updated
                        PLA_IMP: {
                                reg_a = inst.alu_a;
                                reg_result = inst.alu_a;
                                update_z(reg_a);
                                update_n(reg_a);
                        };
                        PLP_IMP: {
                                reg_status = inst.alu_a;
                                reg_status[5:5] = 1; // this is always one
                        };
 
                        ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
                        ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
                        ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
                        ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
                        ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
                        ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
 
                        RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
                        //RTS_IMP: { };
 
                        SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
                        SBC_ZPG: { exec_sub(); };
                        SBC_ZPX: { exec_sub(); };
                        SBC_ABS: { exec_sub(); };
                        SBC_ABX: { exec_sub(); };
                        SBC_ABY: { exec_sub(); };
                        SBC_IDX: { exec_sub(); };
                        SBC_IDY: { exec_sub(); };
 
                        SEC_IMP: { reg_status[0:0] = 1; };
                        SED_IMP: { reg_status[3:3] = 1; };
                        SEI_IMP: { reg_status[2:2] = 1; };
 
                        STA_ZPG: { reg_result = reg_a; };
                        STA_ZPX: { reg_result = reg_a; };
                        STA_ABS: { reg_result = reg_a; };
                        STA_ABX: { reg_result = reg_a; };
                        STA_ABY: { reg_result = reg_a; };
                        STA_IDX: { reg_result = reg_a; };
                        STA_IDY: { reg_result = reg_a; };
                        STX_ZPG: { };
                        STX_ZPY: { };
                        STX_ABS: { };
                        STY_ZPG: { };
                        STY_ZPX: { };
                        STY_ABS: { };
 
                        TAX_IMP: { exec_transfer(reg_a, reg_x); };
                        TAY_IMP: { exec_transfer(reg_a, reg_y); };
                        TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
                        TXA_IMP: { exec_transfer(reg_x, reg_a); };
                        TXS_IMP: { };
                        TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
 
                        // note: tya and txa do not update the result register
 
                        default: {
                                // all the random generated opcodes will fall here
                        }
                };
        };
 
        exec_transfer(source : byte, dest : *byte) is {
                dest = source;
                update_z(dest);
                update_n(dest);
        };
 
        exec_sub() is {
                var temp: int;
 
                temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
                reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
 
                reg_status[7:7] = temp[7:7]; // N
                reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
 
                if (reg_result == 0) {
                        reg_status[1:1] = 1; // Z
                } else {
                        reg_status[1:1] = 0; // Z
                };
 
                if (reg_status[3:3] == 1) { // decimal
                        var op1 : int;
                        var op2 : int;
 
                        op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);
                        op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);
 
                        if (op1[4:4] == 1) {
                                op1 -= 6;
                                op2 = op2 - 1;
                        };
 
                        if(op2[8:8] == 1) {
                              op2 -= 0x60;
                        };
 
                        reg_a = (op1 & 0x0f) | (op2 & 0xf0);
                        reg_result = reg_a;
                }
                else {
                        reg_a = temp.as_a(byte);
                };
 
                if ( (temp & 0xff00) != 0x0000 ) {
                        reg_status[0:0] = 0;
                } else {
                        reg_status[0:0] = 1;
                };
        };
 
        exec_rot(left : bool, arg1 : byte) is {
                var oldcarry : bit;
 
                if (left) {
                        oldcarry = reg_status[0:0];
                        reg_status[0:0] = arg1[7:7];
                        reg_result = arg1 << 1;
                        reg_result[0:0] = oldcarry;
                }
                else {
                        oldcarry = reg_status[0:0];
                        reg_status[0:0] = arg1[0:0];
                        reg_result = arg1 >> 1;
                        reg_result[7:7] = oldcarry;
                };
 
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_or() is {
                reg_a = reg_a | inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_lsr(arg1 : *byte) is {
                reg_status[0:0] = arg1[0:0];
                arg1 = arg1 >> 1;
                update_z(arg1);
                update_n(arg1);
                reg_result = arg1;
        };
 
        exec_load(arg1 : *byte, update_result : bool) is {
                arg1 = inst.alu_a;
 
                if (update_result) { //
                        reg_result = inst.alu_a; // no need for this but...
                };
                update_z(arg1);
                update_n(arg1);
        };
 
        exec_inc(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 + 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { //
                        reg_result = arg1;
                };
        };
 
        exec_eor() is {
                reg_a = reg_a ^ inst.alu_a;
                reg_result = reg_a;
                update_z(reg_a);
                update_n(reg_a);
        };
 
        exec_dec(arg1 : *byte, update_result : bool) is {
                arg1 = arg1 - 1;
                update_z(arg1);
                update_n(arg1);
 
                if (update_result) { // DEX and DEY do not output the result
                        reg_result = arg1;
                };
        };
 
        exec_cmp(arg1 : byte) is {
                update_z(arg1 - inst.alu_a);
                update_n(arg1 - inst.alu_a);
 
                if (arg1 >= inst.alu_a) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                };
        };
 
        exec_bit() is {
                update_z(reg_a & inst.alu_a);
                reg_status[7:7] = inst.alu_a[7:7];
                reg_status[6:6] = inst.alu_a[6:6];
        };
 
        exec_asl_acc() is {
                reg_status[0:0] = reg_a[7:7];
                reg_a = reg_a * 2;
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_asl_mem() is {
                reg_status[0:0] = inst.alu_a[7:7];
                reg_result = inst.alu_a * 2;
                update_z(reg_result);
                update_n(reg_result);
        };
 
        exec_and() is {
                reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
                update_z(reg_a);
                update_n(reg_a);
                reg_result = reg_a;
        };
 
        exec_sum() is {
                //out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
                if (reg_status[3:3] == 1) {
                        var op1 : byte;
                        var op2 : byte;
                        var aux : byte;
 
                        op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
                        //Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
 
                        op2 = reg_a[7:4] + inst.alu_a[7:4];
                        //carry_aux = reg_a[7:4] + inst.alu_a[7:4];
                        //Int32 hi = (A & 0xf0) + (operand & 0xf0);
 
                        aux = op1 + op2;
 
                        if (aux[7:0] == 0) {
                                reg_status[1:1] = 1;
                        }
                        else {
                                reg_status[1:1] = 0;
                        };
                        //notZ = (lo+hi) & 0xff;
 
                        if (op1 > 0x09) {
                                op2 += 0x01;
                                op1 += 0x06;
                        };
 
                        reg_status[7:7] = op2[3:3];
                        //N = hi & 0x80;
 
                        reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
                        //V = ~(A ^ operand) & (A ^ hi) & 0x80;
                        if (op2 > 0x09) {
                                op2 += 0x06;
                        };
                        //if (hi > 0x90) hi += 0x60;
 
                        reg_status[0:0] = (op2 > 15) ? 1 : 0;
                        //C = hi & 0xff00;
 
                        reg_a[3:0] = op1[3:0];
                        reg_a[7:4] = op2[3:0];
                        //reg_a = (lo & 0x0f) + (hi & 0xf0);
 
                        reg_result = reg_a;
                }
                else { // stella checked
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
                        update_n(reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_z(reg_result);
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
 
                        reg_a = reg_result;
                };
        };
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
                if (arg1 + arg2 + arg3 > 255) {
                        reg_status[0:0] = 1;
                }
                else {
                        reg_status[0:0] = 0;
                }
        };
 
        update_v(op1 : byte, op2 : byte, res : byte) is {
                if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
                        reg_status[6:6] = 1;
                }
                else {
                        reg_status[6:6] = 0;
                };
        };
 
        update_z(arg : byte) is {
                if (arg == 0) {
                        reg_status[1:1] = 1;
                }
                else {
                        reg_status[1:1] = 0;
                }
        };
 
 
        update_n(arg : byte) is {
                if (arg[7:7] == 1) {
                        reg_status[7:7] = 1;
                }
                else {
                        reg_status[7:7] = 0;
                }
        };
};
'>

Line No.	Rev	Author	Line
1	131	creep	`alu_chk.e`
2			`<'`
3			`import alu_components;`
4
5			`unit alu_chk_u {`
6			`reg_a : byte;`
7			`reg_x : byte;`
8			`reg_y : byte;`
9			`reg_status : byte;`
10	135	creep	`reg_result : byte;`
11	131	creep
12	159	creep	`!inst : alu_input_s;`
13			`!next_inst : alu_input_s;`
14	132	creep
15	131	creep	`count_cycles : int;`
16			`first_cycle : bool;`
17	159	creep	`last_a : byte;`
18			`last_status : byte;`
19			`last_result : byte;`
20	182	creep	`rst_counter : byte;`
21	131	creep
22			`keep first_cycle == TRUE;`
23			`keep count_cycles == 0;`
24	182	creep	`keep rst_counter == 0;`
25	131	creep
26	182	creep	`event T3_cover_event;`
27			`cover T3_cover_event is {`
28			`item rst_counter; // using num_of_buckets=100;`
29			`};`
30
31
32	131	creep	`store(input : alu_input_s) is {`
33	134	creep	`count_cycles = count_cycles + 1;`
34
35	153	creep	`//out ("CYCLE ", count_cycles, " STORE:");`
36			`//print input;`
37	132	creep
38	159	creep	`last_a = reg_a;`
39			`last_status = reg_status;`
40			`last_result = reg_result;`
41
42	132	creep	`if (first_cycle) {`
43			`inst = input;`
44			`next_inst = input;`
45			`}`
46			`else {`
47			`inst = next_inst;`
48			`next_inst = input;`
49			`};`
50
51	131	creep	`};`
52
53			`compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {`
54			`if (first_cycle) {`
55			`first_cycle = FALSE;`
56	143	creep	`reg_x = 0;`
57			`reg_y = 0;`
58			`reg_status = 8'b00100010;`
59	185	creep	`reg_a = 0;`
60	135	creep	`reg_result = 0;`
61	131	creep	`}`
62	132	creep	`else {`
63	185	creep	`//out ("CYCLE ", count_cycles, " COMPARE:");`
64			`//print inst;`
65	134	creep
66	159	creep	`if (count_cycles == 99999) {`
67			`out("ENOUGH!");`
68			`stop_run();`
69			`};`
70
71	182	creep	`if (inst.input_kind == RESET) {`
72			`rst_counter = rst_counter + 1;`
73			`}`
74			`else {`
75			`emit T3_cover_event;`
76			`rst_counter = 0;`
77			`};`
78
79	132	creep	`case inst.input_kind {`
80			`ENABLED_VALID: {`
81	153	creep	`//out("CYCLE ", count_cycles, ": executing and comparing");`
82	185	creep	`execute(inst.alu_opcode);`
83	132	creep	`};`
84	143	creep	`RESET: {`
85	146	creep	`reg_x = 0;`
86			`reg_y = 0;`
87			`reg_status = 8'b00100010;`
88	235	creep	`reg_a = 0;`
89	146	creep	`reg_result = 0;`
90
91	143	creep	`return;`
92			`};`
93	182	creep	`ENABLED_RAND: {`
94	185	creep	`execute(inst.rand_op.as_a(valid_opcodes));`
95
96			`if (reg_status[3:3] == 1) {`
97			`case inst.rand_op.as_a(valid_opcodes) {`
98			`SBC_IMM: {`
99			`reg_a = alu_result;`
100			`reg_result = alu_result;`
101			`reg_status = alu_status;`
102			`};`
103			`SBC_ZPG: {`
104			`reg_a = alu_result;`
105			`reg_result = alu_result;`
106			`reg_status = alu_status;`
107			`};`
108			`SBC_ZPX: {`
109			`reg_a = alu_result;`
110			`reg_result = alu_result;`
111			`reg_status = alu_status;`
112			`};`
113			`SBC_ABS: {`
114			`reg_a = alu_result;`
115			`reg_result = alu_result;`
116			`reg_status = alu_status;`
117			`};`
118			`SBC_ABX: {`
119			`reg_a = alu_result;`
120			`reg_result = alu_result;`
121			`reg_status = alu_status;`
122			`};`
123			`SBC_ABY: {`
124			`reg_a = alu_result;`
125			`reg_result = alu_result;`
126			`reg_status = alu_status;`
127			`};`
128			`SBC_IDX: {`
129			`reg_a = alu_result;`
130			`reg_result = alu_result;`
131			`reg_status = alu_status;`
132			`};`
133			`SBC_IDY: {`
134			`reg_a = alu_result;`
135			`reg_result = alu_result;`
136			`reg_status = alu_status;`
137			`};`
138			`};`
139			`};`
140
141	182	creep	`};`
142	132	creep	`default: {`
143			`};`
144			`};`
145
146	133	creep	`// here i have already calculated. must compare!`
147	143	creep
148	146	creep	`if ((reg_result != alu_result) \|\| (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {`
149	153	creep	`out("#########################################################");`
150	135	creep	`print me;`
151	155	creep	`print me.inst;`
152	153	creep	`out("#########################################################");`
153	134	creep	`print alu_result;`
154	135	creep	`print alu_status;`
155			`print alu_x;`
156			`print alu_y;`
157
158	133	creep	`dut_error("WRONG!");`
159			`};`
160	146	creep	`};`
161	131	creep	`};`
162	132	creep
163	185	creep	`execute(opcode : valid_opcodes) is {`
164			`case opcode {`
165	132	creep	`ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C`
166			`ADC_ZPG: { exec_sum(); };`
167			`ADC_ZPX: { exec_sum(); };`
168			`ADC_ABS: { exec_sum(); };`
169			`ADC_ABX: { exec_sum(); };`
170			`ADC_ABY: { exec_sum(); };`
171			`ADC_IDX: { exec_sum(); };`
172			`ADC_IDY: { exec_sum(); };`
173
174	133	creep	`AND_IMM: { exec_and(); }; // A,Z,N = A&M`
175	132	creep	`AND_ZPG: { exec_and(); };`
176			`AND_ZPX: { exec_and(); };`
177			`AND_ABS: { exec_and(); };`
178			`AND_ABX: { exec_and(); };`
179			`AND_ABY: { exec_and(); };`
180			`AND_IDX: { exec_and(); };`
181			`AND_IDY: { exec_and(); };`
182
183	135	creep	`ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2`
184	132	creep
185	135	creep	`ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2`
186			`ASL_ZPX: { exec_asl_mem(); };`
187			`ASL_ABS: { exec_asl_mem(); };`
188			`ASL_ABX: { exec_asl_mem(); };`
189
190	240	creep	`//BCC_REL: {}; // nothing is done. these are all branches.`
191			`//BCS_REL: {};`
192			`//BEQ_REL: {};`
193			`//BMI_REL: {};`
194			`//BNE_REL: {};`
195			`//BPL_REL: {};`
196			`//BVC_REL: {};`
197			`//BVS_REL: {};`
198	153	creep
199	155	creep	`BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6`
200			`BIT_ABS: { exec_bit(); };`
201
202			`BRK_IMP: { reg_status[4:4] = 1; };`
203
204			`CLC_IMP: { reg_status[0:0] = 0; };`
205			`CLD_IMP: { reg_status[3:3] = 0; };`
206			`CLI_IMP: { reg_status[2:2] = 0; };`
207			`CLV_IMP: { reg_status[6:6] = 0; };`
208
209	159	creep	`CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M`
210			`CMP_ZPG: { exec_cmp(reg_a); };`
211			`CMP_ZPX: { exec_cmp(reg_a); };`
212			`CMP_ABS: { exec_cmp(reg_a); };`
213			`CMP_ABX: { exec_cmp(reg_a); };`
214			`CMP_ABY: { exec_cmp(reg_a); };`
215			`CMP_IDX: { exec_cmp(reg_a); };`
216			`CMP_IDY: { exec_cmp(reg_a); };`
217
218			`CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M`
219			`CPX_ZPG: { exec_cmp(reg_x); };`
220			`CPX_ABS: { exec_cmp(reg_x); };`
221
222			`CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M`
223			`CPY_ZPG: { exec_cmp(reg_y); };`
224			`CPY_ABS: { exec_cmp(reg_y); };`
225
226			`DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1`
227			`DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };`
228			`DEC_ABS: { exec_dec(inst.alu_a, TRUE); };`
229			`DEC_ABX: { exec_dec(inst.alu_a, TRUE); };`
230
231			`DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1`
232			`DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1`
233
234			`EOR_IMM: { exec_eor(); }; // A,Z,N = A^M`
235			`EOR_ZPG: { exec_eor(); };`
236			`EOR_ZPX: { exec_eor(); };`
237			`EOR_ABS: { exec_eor(); };`
238			`EOR_ABX: { exec_eor(); };`
239			`EOR_ABY: { exec_eor(); };`
240			`EOR_IDX: { exec_eor(); };`
241			`EOR_IDY: { exec_eor(); };`
242
243			`INC_ZPG: { exec_inc(inst.alu_a, TRUE); };`
244			`INC_ZPX: { exec_inc(inst.alu_a, TRUE); };`
245			`INC_ABS: { exec_inc(inst.alu_a, TRUE); };`
246			`INC_ABX: { exec_inc(inst.alu_a, TRUE); };`
247
248			`INX_IMP: { exec_inc(reg_x, FALSE); };`
249			`INY_IMP: { exec_inc(reg_y, FALSE); };`
250
251	240	creep	`//JMP_ABS: {};`
252			`//JMP_IND: {};`
253			`//JSR_ABS: {};`
254	159	creep
255			`LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M`
256			`LDA_ZPG: { exec_load(reg_a, TRUE); };`
257			`LDA_ZPX: { exec_load(reg_a, TRUE); };`
258			`LDA_ABS: { exec_load(reg_a, TRUE); };`
259			`LDA_ABX: { exec_load(reg_a, TRUE); };`
260			`LDA_ABY: { exec_load(reg_a, TRUE); };`
261			`LDA_IDX: { exec_load(reg_a, TRUE); };`
262			`LDA_IDY: { exec_load(reg_a, TRUE); };`
263
264			`LDX_IMM: { exec_load(reg_x, FALSE); };`
265			`LDX_ZPG: { exec_load(reg_x, FALSE); };`
266			`LDX_ZPY: { exec_load(reg_x, FALSE); };`
267			`LDX_ABS: { exec_load(reg_x, FALSE); };`
268			`LDX_ABY: { exec_load(reg_x, FALSE); };`
269
270			`LDY_IMM: { exec_load(reg_y, FALSE); };`
271			`LDY_ZPG: { exec_load(reg_y, FALSE); };`
272			`LDY_ZPX: { exec_load(reg_y, FALSE); };`
273			`LDY_ABS: { exec_load(reg_y, FALSE); };`
274			`LDY_ABX: { exec_load(reg_y, FALSE); };`
275
276			`LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2`
277			`LSR_ZPG: { exec_lsr(inst.alu_a); };`
278			`LSR_ZPX: { exec_lsr(inst.alu_a); };`
279			`LSR_ABS: { exec_lsr(inst.alu_a); };`
280			`LSR_ABX: { exec_lsr(inst.alu_a); };`
281
282	240	creep	`//NOP_IMP: {};`
283	159	creep
284			`ORA_IMM: { exec_or(); }; // A,Z,N = A\|M`
285			`ORA_ZPG: { exec_or(); };`
286			`ORA_ZPX: { exec_or(); };`
287			`ORA_ABS: { exec_or(); };`
288			`ORA_ABX: { exec_or(); };`
289			`ORA_ABY: { exec_or(); };`
290			`ORA_IDX: { exec_or(); };`
291			`ORA_IDY: { exec_or(); };`
292
293			`PHA_IMP: { reg_result = reg_a; };`
294	240	creep	`//PHP_IMP: {}; // P is always connected and the result is not updated`
295	159	creep	`PLA_IMP: {`
296			`reg_a = inst.alu_a;`
297			`reg_result = inst.alu_a;`
298			`update_z(reg_a);`
299			`update_n(reg_a);`
300			`};`
301			`PLP_IMP: {`
302			`reg_status = inst.alu_a;`
303			`reg_status[5:5] = 1; // this is always one`
304			`};`
305
306	185	creep	`ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };`
307	177	creep	`ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };`
308			`ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };`
309			`ROL_ABS: { exec_rot(TRUE, inst.alu_a); };`
310			`ROL_ABX: { exec_rot(TRUE, inst.alu_a); };`
311	185	creep	`ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };`
312	177	creep	`ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };`
313			`ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };`
314			`ROR_ABS: { exec_rot(FALSE, inst.alu_a); };`
315			`ROR_ABX: { exec_rot(FALSE, inst.alu_a); };`
316	160	creep
317	177	creep	`RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };`
318	240	creep	`//RTS_IMP: { };`
319	177	creep
320			`SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)`
321			`SBC_ZPG: { exec_sub(); };`
322			`SBC_ZPX: { exec_sub(); };`
323			`SBC_ABS: { exec_sub(); };`
324			`SBC_ABX: { exec_sub(); };`
325			`SBC_ABY: { exec_sub(); };`
326			`SBC_IDX: { exec_sub(); };`
327			`SBC_IDY: { exec_sub(); };`
328
329			`SEC_IMP: { reg_status[0:0] = 1; };`
330			`SED_IMP: { reg_status[3:3] = 1; };`
331			`SEI_IMP: { reg_status[2:2] = 1; };`
332
333			`STA_ZPG: { reg_result = reg_a; };`
334			`STA_ZPX: { reg_result = reg_a; };`
335			`STA_ABS: { reg_result = reg_a; };`
336			`STA_ABX: { reg_result = reg_a; };`
337			`STA_ABY: { reg_result = reg_a; };`
338			`STA_IDX: { reg_result = reg_a; };`
339			`STA_IDY: { reg_result = reg_a; };`
340	182	creep	`STX_ZPG: { };`
341			`STX_ZPY: { };`
342			`STX_ABS: { };`
343			`STY_ZPG: { };`
344			`STY_ZPX: { };`
345			`STY_ABS: { };`
346	177	creep
347	182	creep	`TAX_IMP: { exec_transfer(reg_a, reg_x); };`
348			`TAY_IMP: { exec_transfer(reg_a, reg_y); };`
349			`TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };`
350			`TXA_IMP: { exec_transfer(reg_x, reg_a); };`
351			`TXS_IMP: { };`
352	185	creep	`TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y`
353	177	creep
354	185	creep	`// note: tya and txa do not update the result register`
355
356	132	creep	`default: {`
357	182	creep	`// all the random generated opcodes will fall here`
358	132	creep	`}`
359			`};`
360			`};`
361
362	177	creep	`exec_transfer(source : byte, dest : *byte) is {`
363			`dest = source;`
364			`update_z(dest);`
365			`update_n(dest);`
366			`};`
367
368			`exec_sub() is {`
369	235	creep	`var temp: int;`
370
371			`temp = reg_a - inst.alu_a - 1 + reg_status[0:0];`
372			`reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];`
373
374			`reg_status[7:7] = temp[7:7]; // N`
375			`reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V`
376
377			`if (reg_result == 0) {`
378			`reg_status[1:1] = 1; // Z`
379			`} else {`
380			`reg_status[1:1] = 0; // Z`
381			`};`
382
383	233	creep	`if (reg_status[3:3] == 1) { // decimal`
384	177	creep	`var op1 : int;`
385			`var op2 : int;`
386
387	235	creep	`op1 = (reg_a & 0x0f ) - (inst.alu_a & 0x0f) - ( (reg_status[0:0] == 1) ? 0 : 1);`
388			`op2 = (reg_a & 0xf0) - (inst.alu_a & 0xf0);`
389	185	creep
390	235	creep	`if (op1[4:4] == 1) {`
391			`op1 -= 6;`
392			`op2 = op2 - 1;`
393	177	creep	`};`
394	235	creep
395			`if(op2[8:8] == 1) {`
396			`op2 -= 0x60;`
397			`};`
398	177	creep
399	235	creep	`reg_a = (op1 & 0x0f) \| (op2 & 0xf0);`
400			`reg_result = reg_a;`
401	177	creep	`}`
402			`else {`
403	233	creep	`reg_a = temp.as_a(byte);`
404	177	creep	`};`
405	235	creep
406			`if ( (temp & 0xff00) != 0x0000 ) {`
407			`reg_status[0:0] = 0;`
408			`} else {`
409			`reg_status[0:0] = 1;`
410			`};`
411	177	creep	`};`
412
413	185	creep	`exec_rot(left : bool, arg1 : byte) is {`
414	160	creep	`var oldcarry : bit;`
415
416	177	creep	`if (left) {`
417			`oldcarry = reg_status[0:0];`
418			`reg_status[0:0] = arg1[7:7];`
419	185	creep	`reg_result = arg1 << 1;`
420			`reg_result[0:0] = oldcarry;`
421	177	creep	`}`
422			`else {`
423			`oldcarry = reg_status[0:0];`
424			`reg_status[0:0] = arg1[0:0];`
425	185	creep	`reg_result = arg1 >> 1;`
426			`reg_result[7:7] = oldcarry;`
427	177	creep	`};`
428	160	creep
429	185	creep	`update_z(reg_result);`
430			`update_n(reg_result);`
431	160	creep	`};`
432
433	159	creep	`exec_or() is {`
434			`reg_a = reg_a \| inst.alu_a;`
435			`reg_result = reg_a;`
436			`update_z(reg_a);`
437			`update_n(reg_a);`
438			`};`
439
440			`exec_lsr(arg1 : *byte) is {`
441			`reg_status[0:0] = arg1[0:0];`
442			`arg1 = arg1 >> 1;`
443			`update_z(arg1);`
444			`update_n(arg1);`
445			`reg_result = arg1;`
446			`};`
447
448			`exec_load(arg1 : *byte, update_result : bool) is {`
449			`arg1 = inst.alu_a;`
450
451			`if (update_result) { //`
452			`reg_result = inst.alu_a; // no need for this but...`
453			`};`
454			`update_z(arg1);`
455			`update_n(arg1);`
456			`};`
457
458			`exec_inc(arg1 : *byte, update_result : bool) is {`
459			`arg1 = arg1 + 1;`
460			`update_z(arg1);`
461			`update_n(arg1);`
462
463			`if (update_result) { //`
464			`reg_result = arg1;`
465			`};`
466			`};`
467
468			`exec_eor() is {`
469			`reg_a = reg_a ^ inst.alu_a;`
470			`reg_result = reg_a;`
471			`update_z(reg_a);`
472			`update_n(reg_a);`
473			`};`
474
475			`exec_dec(arg1 : *byte, update_result : bool) is {`
476			`arg1 = arg1 - 1;`
477			`update_z(arg1);`
478			`update_n(arg1);`
479
480			`if (update_result) { // DEX and DEY do not output the result`
481			`reg_result = arg1;`
482			`};`
483			`};`
484
485			`exec_cmp(arg1 : byte) is {`
486			`update_z(arg1 - inst.alu_a);`
487			`update_n(arg1 - inst.alu_a);`
488
489			`if (arg1 >= inst.alu_a) {`
490			`reg_status[0:0] = 1;`
491			`}`
492			`else {`
493			`reg_status[0:0] = 0;`
494			`};`
495			`};`
496
497	155	creep	`exec_bit() is {`
498			`update_z(reg_a & inst.alu_a);`
499			`reg_status[7:7] = inst.alu_a[7:7];`
500			`reg_status[6:6] = inst.alu_a[6:6];`

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