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[/] [t6507lp/] [trunk/] [fv/] [fsm_chk.e] - Blame information for rev 214

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<'
import fsm_components;
type state_t : [RESET, CYCLE_1, CYCLE_2, CYCLE_3, CYCLE_4, CYCLE_5, CYCLE_6, CYCLE_7];
unit fsm_chk_u {
        !A  : byte;
          keep soft A == 0;
        !X  : byte;
          keep soft X == 0;
        !Y  : byte;
          keep soft Y == 0;
        !PC : uint(bits : 13);
          keep soft PC == 0;
//      !SP : uint(bits : 9);
//        keep soft SP == 9'b100000000;
        !SP : byte;
          keep soft SP == 0;
        !pointer : byte;
          keep soft pointer == 0;
 
        !more_cycles : bool;
          keep soft more_cycles == FALSE;
        --!R  : byte;
        -- keep soft R == 0;
        --!PS : byte;
        --  keep soft PS[0:0] == 0;
        --  keep soft PS[1:1] == 0;
        --  keep soft PS[2:2] == 0;
        --  keep soft PS[3:3] == 0;
        --  keep soft PS[4:4] == 0;
        --  keep soft PS[5:5] == 1;
        --  keep soft PS[6:6] == 0;
        --  keep soft PS[7:7] == 0;
        -- N : bit;
        -- V : bit;
        -- B : bit;
        -- D : bit;
        -- I : bit;
        -- Z : bit;
        -- C : bit;
        -- keep soft N == 0;
        -- keep soft V == 0;
        -- keep soft B == 0;
        -- keep soft D == 0;
        -- keep soft I == 0;
        -- keep soft Z == 0;
        -- keep soft C == 0;
 
        !new_inst   : bool;
        keep new_inst == FALSE;
        !new_input : fsm_input_s;
        !old_input : fsm_input_s;
        --!new_inst  : bool;
        --keep soft new_inst == FALSE;
 
        --!i : ps_index;
 
        !new_state : state_t;
        !old_state : state_t;
 
        --count_cycles : int;
        --first_cycle  : bool;
        --last_a       : byte;
        --last_status  : byte;
        --last_result  : byte;
        !PCL:byte;
        !PCH:byte;
        !SP_aux:byte;
        !rst : bit;
        !rst_counter  : byte;
 
        --keep first_cycle  == TRUE;
        --keep count_cycles == 0;
        keep rst_counter  == 0;
 
        !instruction      : valid_opcodes;
        !last_instruction : valid_opcodes;
        !instructions     : valid_opcodes;
 
        print_state () is {
                outf("-------------------------------------------------------\n");
                print instructions;
                -- print instruction;
                print 't6507lp_fsm.ir';
                print 't6507lp_fsm.sp';
                print SP + 256;
                print 't6507lp_fsm.pc';
                print PC;
                --print addr;
                case ('t6507lp_fsm.state') {
 
                        2  : { outf("  t6507lp_fsm.state = FETCH_LOW\n");};
                        3  : { outf("  t6507lp_fsm.state = FETCH_HIGH\n"); };
                        4  : { outf("  t6507lp_fsm.state = READ_MEM\n"); };
                        5  : { outf("  t6507lp_fsm.state = DUMMY_WRT_CALC\n"); };
                        6  : { outf("  t6507lp_fsm.state = WRITE_MEM\n"); };
                        7  : { outf("  t6507lp_fsm.state = FETCH_OP_CALC_PARAM\n"); };
                        8  : { outf("  t6507lp_fsm.state = READ_MEM_CALC_INDEX\n"); };
                        9  : { outf("  t6507lp_fsm.state = FETCH_HIGH_CALC_INDEX\n"); };
                        10 : { outf("  t6507lp_fsm.state = READ_MEM_FIX_ADDR\n"); };
                        11 : { outf("  t6507lp_fsm.state = FETCH_OP_EVAL_BRANCH\n"); };
                        12 : { outf("  t6507lp_fsm.state = FETCH_OP_FIX_PC\n"); };
                        13 : { outf("  t6507lp_fsm.state = READ_FROM_POINTER\n"); };
                        14 : { outf("  t6507lp_fsm.state = READ_FROM_POINTER_X\n"); };
                        15 : { outf("  t6507lp_fsm.state = READ_FROM_POINTER_X1\n"); };
                        16 : { outf("  t6507lp_fsm.state = PUSH_PCH\n"); };
                        17 : { outf("  t6507lp_fsm.state = PUSH_PCL\n"); };
                        18 : { outf("  t6507lp_fsm.state = PUSH_STATUS\n"); };
                        19 : { outf("  t6507lp_fsm.state = FETCH_PCL\n"); };
                        20 : { outf("  t6507lp_fsm.state = FETCH_PCH\n"); };
                        21 : { outf("  t6507lp_fsm.state = INCREMENT_SP\n"); };
                        22 : { outf("  t6507lp_fsm.state = PULL_STATUS\n"); };
                        23 : { outf("  t6507lp_fsm.state = PULL_PCL\n"); };
                        24 : { outf("  t6507lp_fsm.state = PULL_PCH\n"); };
                        25 : { outf("  t6507lp_fsm.state = INCREMENT_PC\n"); };
                        26 : { outf("  t6507lp_fsm.state = PUSH_REGISTER\n"); };
                        27 : { outf("  t6507lp_fsm.state = PULL_REGISTER\n"); };
                        28 : { outf("  t6507lp_fsm.state = DUMMY\n"); };
                        31 : { outf("  t6507lp_fsm.state = RESET\n"); };
                };
        };
 
        store(input : fsm_input_s) is {
        --reset_n    : bit;
        --alu_result : byte;
        --alu_status : byte;
        --data_in    : byte;
        --alu_x      : byte;
        --alu_y      : byte;
        //print me;
        //print input;
                if (input.reset_n == 0) {
                  rst_counter = 0;
                  new_state = RESET;
                  old_state = RESET;
                  A = 0;
                  X = 0;
                  Y = 0;
                  PC = 0;
                  SP = 255;
                }
                else {
                        case (old_state) {
                                RESET    : {
                                        if (rst_counter == 7) {
                                                new_state = CYCLE_1;
                                        };
                                };
                                CYCLE_1 : {
                                        instruction = input.data_in.as_a(valid_opcodes);
                                        new_state = CYCLE_2;
                                };
                                CYCLE_2 : {
                                        X = input.alu_x;
                                        Y = input.alu_y;
                                        case {
                                                (
                                                  instruction == BRK_IMP ||
                                                  instruction == PHA_IMP ||
                                                  instruction == PHP_IMP ||
                                                  instruction == PLA_IMP ||
                                                  instruction == PLP_IMP ||
                                                  instruction == RTI_IMP ||
                                                  instruction == RTS_IMP
                                                ) : {
                                                        new_state = CYCLE_3;
                                                };
                                                //JSR_ABS : {
                                                //      new_state = CYCLE_3;
                                                //      PCL = input.data_in;
                                                //};
                                                (
                                                  instruction == ADC_ABS ||
                                                  instruction == ASL_ABS ||
                                                  instruction == BIT_ABS ||
                                                  instruction == AND_ABS ||
                                                  instruction == CMP_ABS ||
                                                  instruction == DEC_ABS ||
                                                  instruction == EOR_ABS ||
                                                  instruction == INC_ABS ||
                                                  instruction == JMP_ABS ||
                                                  instruction == LDA_ABS ||
                                                  instruction == LDX_ABS ||
                                                  instruction == LDY_ABS ||
                                                  instruction == LSR_ABS ||
                                                  instruction == ORA_ABS ||
                                                  instruction == ROL_ABS ||
                                                  instruction == ROR_ABS ||
                                                  instruction == SBC_ABS ||
                                                  instruction == STA_ABS ||
                                                  instruction == STX_ABS ||
                                                  instruction == STY_ABS ||
                                                  instruction == LDA_ZPG ||
                                                  instruction == LDX_ZPG ||
                                                  instruction == LDY_ZPG ||
                                                  instruction == EOR_ZPG ||
                                                  instruction == AND_ZPG ||
                                                  instruction == ORA_ZPG ||
                                                  instruction == ADC_ZPG ||
                                                  instruction == SBC_ZPG ||
                                                  instruction == CMP_ZPG ||
                                                  instruction == BIT_ZPG ||
                                                  instruction == STA_ZPG ||
                                                  instruction == STX_ZPG ||
                                                  instruction == STY_ZPG ||
                                                  instruction == ASL_ZPG ||
                                                  instruction == LSR_ZPG ||
                                                  instruction == ROL_ZPG ||
                                                  instruction == ROR_ZPG ||
                                                  instruction == INC_ZPG ||
                                                  instruction == DEC_ZPG ||
                                                  instruction == LDA_ZPX ||
                                                  instruction == LDX_ZPY ||
                                                  instruction == LDY_ZPX ||
                                                  instruction == EOR_ZPX ||
                                                  instruction == AND_ZPX ||
                                                  instruction == ORA_ZPX ||
                                                  instruction == ADC_ZPX ||
                                                  instruction == SBC_ZPX ||
                                                  instruction == CMP_ZPX ||
                                                  instruction == ASL_ZPX ||
                                                  instruction == LSR_ZPX ||
                                                  instruction == ROL_ZPX ||
                                                  instruction == ROR_ZPX ||
                                                  instruction == INC_ZPX ||
                                                  instruction == DEC_ZPX ||
                                                  instruction == STA_ZPX ||
                                                  instruction == STX_ZPY ||
                                                  instruction == STY_ZPX ||
                                                  instruction == LDA_ABX ||
                                                  instruction == LDA_ABY ||
                                                  instruction == LDX_ABY ||
                                                  instruction == LDY_ABX ||
                                                  instruction == EOR_ABX ||
                                                  instruction == EOR_ABY ||
                                                  instruction == AND_ABX ||
                                                  instruction == AND_ABY ||
                                                  instruction == ORA_ABX ||
                                                  instruction == ORA_ABY ||
                                                  instruction == ADC_ABX ||
                                                  instruction == ADC_ABY ||
                                                  instruction == SBC_ABX ||
                                                  instruction == SBC_ABY ||
                                                  instruction == CMP_ABX ||
                                                  instruction == CMP_ABY ||
                                                  instruction == ASL_ABX ||
                                                  instruction == LSR_ABX ||
                                                  instruction == ROL_ABX ||
                                                  instruction == ROR_ABX ||
                                                  instruction == INC_ABX ||
                                                  instruction == DEC_ABX
                                                ) : {
                                                        new_state = CYCLE_3;
                                                        PCL = input.data_in;
                                                };
                                                (
                                                  instruction == LDA_IDX ||
                                                  instruction == STA_IDX ||
                                                  instruction == ORA_IDX ||
                                                  instruction == EOR_IDX ||
                                                  instruction == AND_IDX ||
                                                  instruction == ADC_IDX ||
                                                  instruction == CMP_IDX ||
                                                  instruction == SBC_IDX
                                                ) : {
                                                        new_state = CYCLE_3;
                                                        pointer = input.data_in;
                                                };
                                                (
                                                  instruction == TXS_IMP
                                                ) : {
                                                        new_state = CYCLE_1;
                                                        SP_aux    = input.alu_x;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                                CYCLE_3 : {
                                        case {
                                                //JSR_ABS : {
                                                //      new_state = CYCLE_4;
                                                //      PCH = input.data_in;
                                                //};
                                                (
                                                  instruction == BRK_IMP ||
                                                  instruction == PLA_IMP ||
                                                  instruction == PLP_IMP ||
                                                  instruction == RTI_IMP ||
                                                  instruction == RTS_IMP ||
                                                  instruction == ASL_ZPG ||
                                                  instruction == LSR_ZPG ||
                                                  instruction == ROL_ZPG ||
                                                  instruction == ROR_ZPG ||
                                                  instruction == INC_ZPG ||
                                                  instruction == DEC_ZPG ||
                                                  instruction == LDA_ZPX ||
                                                  instruction == LDX_ZPY ||
                                                  instruction == LDY_ZPX ||
                                                  instruction == EOR_ZPX ||
                                                  instruction == AND_ZPX ||
                                                  instruction == ORA_ZPX ||
                                                  instruction == ADC_ZPX ||
                                                  instruction == SBC_ZPX ||
                                                  instruction == CMP_ZPX ||
                                                  instruction == ASL_ZPX ||
                                                  instruction == LSR_ZPX ||
                                                  instruction == ROL_ZPX ||
                                                  instruction == ROR_ZPX ||
                                                  instruction == INC_ZPX ||
                                                  instruction == DEC_ZPX ||
                                                  instruction == STA_ZPX ||
                                                  instruction == STX_ZPY ||
                                                  instruction == STY_ZPX ||
                                                  instruction == LDA_IDX ||
                                                  instruction == STA_IDX ||
                                                  instruction == ORA_IDX ||
                                                  instruction == EOR_IDX ||
                                                  instruction == AND_IDX ||
                                                  instruction == ADC_IDX ||
                                                  instruction == CMP_IDX ||
                                                  instruction == SBC_IDX
                                                ) : {
                                                        new_state = CYCLE_4;
                                                };
                                                (
                                                  instruction == ADC_ABS ||
                                                  instruction == ASL_ABS ||
                                                  instruction == BIT_ABS ||
                                                  instruction == AND_ABS ||
                                                  instruction == CMP_ABS ||
                                                  instruction == DEC_ABS ||
                                                  instruction == EOR_ABS ||
                                                  instruction == INC_ABS ||
                                                  instruction == LDA_ABS ||
                                                  instruction == LDX_ABS ||
                                                  instruction == LDY_ABS ||
                                                  instruction == LSR_ABS ||
                                                  instruction == ORA_ABS ||
                                                  instruction == ROL_ABS ||
                                                  instruction == ROR_ABS ||
                                                  instruction == SBC_ABS ||
                                                  instruction == STA_ABS ||
                                                  instruction == STX_ABS ||
                                                  instruction == STY_ABS ||
                                                  instruction == LDA_ABX ||
                                                  instruction == LDA_ABY ||
                                                  instruction == LDX_ABY ||
                                                  instruction == LDY_ABX ||
                                                  instruction == EOR_ABX ||
                                                  instruction == EOR_ABY ||
                                                  instruction == AND_ABX ||
                                                  instruction == AND_ABY ||
                                                  instruction == ORA_ABX ||
                                                  instruction == ORA_ABY ||
                                                  instruction == ADC_ABX ||
                                                  instruction == ADC_ABY ||
                                                  instruction == SBC_ABX ||
                                                  instruction == SBC_ABY ||
                                                  instruction == CMP_ABX ||
                                                  instruction == CMP_ABY ||
                                                  instruction == ASL_ABX ||
                                                  instruction == LSR_ABX ||
                                                  instruction == ROL_ABX ||
                                                  instruction == ROR_ABX ||
                                                  instruction == INC_ABX ||
                                                  instruction == DEC_ABX
                                                ) : {
                                                        new_state = CYCLE_4;
                                                        PCH = input.data_in;
                                                };
                                                (
                                                  instruction == JMP_ABS
                                                ) : {
                                                        new_state = CYCLE_1;
                                                        PCH = input.data_in;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                                CYCLE_4 : {
                                        case {
                                                //JSR_ABS : {
                                                //      new_state = CYCLE_5;
                                                //};
                                                (
                                                  instruction == RTS_IMP
                                                ) : {
                                                        new_state = CYCLE_5;
                                                        PCL = input.data_in;
                                                };
                                                (
                                                  instruction == ASL_ABS ||
                                                  instruction == BRK_IMP ||
                                                  instruction == DEC_ABS ||
                                                  instruction == INC_ABS ||
                                                  instruction == LSR_ABS ||
                                                  instruction == ROL_ABS ||
                                                  instruction == ROR_ABS ||
                                                  instruction == RTI_IMP ||
                                                  instruction == ASL_ZPG ||
                                                  instruction == LSR_ZPG ||
                                                  instruction == ROL_ZPG ||
                                                  instruction == ROR_ZPG ||
                                                  instruction == INC_ZPG ||
                                                  instruction == DEC_ZPG ||
                                                  instruction == ASL_ZPX ||
                                                  instruction == LSR_ZPX ||
                                                  instruction == ROL_ZPX ||
                                                  instruction == ROR_ZPX ||
                                                  instruction == INC_ZPX ||
                                                  instruction == DEC_ZPX ||
                                                  instruction == ASL_ABX ||
                                                  instruction == LSR_ABX ||
                                                  instruction == ROL_ABX ||
                                                  instruction == ROR_ABX ||
                                                  instruction == INC_ABX ||
                                                  instruction == DEC_ABX ||
                                                  (
                                                        more_cycles == TRUE &&
                                                        (
                                                          instruction == LDA_ABX ||
                                                          instruction == LDA_ABY ||
                                                          instruction == LDX_ABY ||
                                                          instruction == LDY_ABX ||
                                                          instruction == EOR_ABX ||
                                                          instruction == EOR_ABY ||
                                                          instruction == AND_ABX ||
                                                          instruction == AND_ABY ||
                                                          instruction == ORA_ABX ||
                                                          instruction == ORA_ABY ||
                                                          instruction == ADC_ABX ||
                                                          instruction == ADC_ABY ||
                                                          instruction == SBC_ABX ||
                                                          instruction == SBC_ABY ||
                                                          instruction == CMP_ABX ||
                                                          instruction == CMP_ABY
                                                        )
                                                  )
                                                ) : {
                                                        new_state = CYCLE_5;
                                                };
                                                (
                                                  instruction == LDA_IDX ||
                                                  instruction == STA_IDX ||
                                                  instruction == ORA_IDX ||
                                                  instruction == EOR_IDX ||
                                                  instruction == AND_IDX ||
                                                  instruction == ADC_IDX ||
                                                  instruction == CMP_IDX ||
                                                  instruction == SBC_IDX
                                                ) : {
                                                        new_state = CYCLE_5;
                                                        PCL = input.data_in;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                                CYCLE_5 : {
                                        case {
                                                //JSR_ABS : {
                                                //      new_state = CYCLE_6;
                                                //};
                                                (
                                                  instruction == RTI_IMP
                                                ) : {
                                                        new_state = CYCLE_6;
                                                        PCL = input.data_in;
                                                };
                                                (
                                                  instruction == RTS_IMP
                                                ) : {
                                                        new_state = CYCLE_6;
                                                        PCH = input.data_in;
                                                };
                                                (
                                                  instruction == ASL_ABS ||
                                                  instruction == BRK_IMP ||
                                                  instruction == DEC_ABS ||
                                                  instruction == INC_ABS ||
                                                  instruction == LSR_ABS ||
                                                  instruction == ROL_ABS ||
                                                  instruction == ROR_ABS ||
                                                  instruction == ASL_ZPX ||
                                                  instruction == LSR_ZPX ||
                                                  instruction == ROL_ZPX ||
                                                  instruction == ROR_ZPX ||
                                                  instruction == INC_ZPX ||
                                                  instruction == DEC_ZPX ||
                                                  instruction == ASL_ABX ||
                                                  instruction == LSR_ABX ||
                                                  instruction == ROL_ABX ||
                                                  instruction == ROR_ABX ||
                                                  instruction == INC_ABX ||
                                                  instruction == DEC_ABX
                                                ) : {
                                                        new_state = CYCLE_6;
                                                };
                                                (
                                                  instruction == LDA_IDX ||
                                                  instruction == STA_IDX ||
                                                  instruction == ORA_IDX ||
                                                  instruction == EOR_IDX ||
                                                  instruction == AND_IDX ||
                                                  instruction == ADC_IDX ||
                                                  instruction == CMP_IDX ||
                                                  instruction == SBC_IDX
                                                ) : {
                                                        new_state = CYCLE_6;
                                                        PCH = input.data_in;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                                CYCLE_6 : {
                                        case {
                                                (
                                                  instruction == BRK_IMP
                                                ) : {
                                                        new_state = CYCLE_7;
                                                        PCL = input.data_in;
                                                };
                                                (
                                                  instructions == RTI_IMP
                                                ) : {
                                                        new_state = CYCLE_1;
                                                        PCH = input.data_in;
                                                };
                                                (
                                                  instruction == ASL_ABX ||
                                                  instruction == LSR_ABX ||
                                                  instruction == ROL_ABX ||
                                                  instruction == ROR_ABX ||
                                                  instruction == INC_ABX ||
                                                  instruction == DEC_ABX
                                                ) : {
                                                        new_state = CYCLE_7;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                                CYCLE_7 : {
                                        case (instruction) {
                                                BRK_IMP : {
                                                        new_state = CYCLE_1;
                                                        PCH = input.data_in;
                                                };
                                                default : {
                                                        new_state = CYCLE_1;
                                                };
                                        };
                                };
                        };
                        old_input = new_input;
                        new_input = input;
                };
        };
 
        compare(addr: uint(bits:13), mem_rw:bit, data_out:byte, alu_opcode:valid_opcodes, alu_a:byte, alu_enable:bit) is {
                case (old_state) {
                        RESET    : {
                                print_state();
                                rst = 1;
                                rst_counter = rst_counter + 1;
                        };
                        CYCLE_1 : {
                                more_cycles = FALSE;
                                print_state();
                                print addr;
                                last_instruction = instructions;
                                instructions = instruction;
                                if (mem_rw != 0) {
                                        dut_error("Mem_rw is Wrong!");
                                };
                                if (rst == 0) {
                                        case {
                                                (
                                                  last_instruction == ADC_ABS ||
                                                  last_instruction == ADC_IMM ||
                                                  last_instruction == AND_ABS ||
                                                  last_instruction == AND_IMM ||
                                                  last_instruction == BIT_ABS ||
                                                  last_instruction == CMP_ABS ||
                                                  last_instruction == CMP_IMM ||
                                                  last_instruction == CPX_IMM ||
                                                  last_instruction == CPY_IMM ||
                                                  last_instruction == EOR_ABS ||
                                                  last_instruction == EOR_IMM ||
                                                  last_instruction == LDA_ABS ||
                                                  last_instruction == LDA_IMM ||
                                                  last_instruction == LDX_ABS ||
                                                  last_instruction == LDX_IMM ||
                                                  last_instruction == LDY_ABS ||
                                                  last_instruction == LDY_IMM ||
                                                  last_instruction == ORA_ABS ||
                                                  last_instruction == ORA_IMM ||
                                                  last_instruction == PLA_IMP ||
                                                  last_instruction == PLP_IMP ||
                                                  last_instruction == SBC_ABS ||
                                                  last_instruction == SBC_IMM ||
                                                  last_instruction == LDA_ZPG ||
                                                  last_instruction == LDX_ZPG ||
                                                  last_instruction == LDY_ZPG ||
                                                  last_instruction == EOR_ZPG ||
                                                  last_instruction == AND_ZPG ||
                                                  last_instruction == ORA_ZPG ||
                                                  last_instruction == ADC_ZPG ||
                                                  last_instruction == SBC_ZPG ||
                                                  last_instruction == CMP_ZPG ||
                                                  last_instruction == BIT_ZPG ||
                                                  last_instruction == LDA_ZPX ||
                                                  last_instruction == LDX_ZPY ||
                                                  last_instruction == LDY_ZPX ||
                                                  last_instruction == EOR_ZPX ||
                                                  last_instruction == AND_ZPX ||
                                                  last_instruction == ORA_ZPX ||
                                                  last_instruction == ADC_ZPX ||
                                                  last_instruction == SBC_ZPX ||
                                                  last_instruction == CMP_ZPX ||
                                                  last_instruction == LDA_ABX ||
                                                  last_instruction == LDA_ABY ||
                                                  last_instruction == LDX_ABY ||
                                                  last_instruction == LDY_ABX ||
                                                  last_instruction == EOR_ABX ||
                                                  last_instruction == EOR_ABY ||
                                                  last_instruction == AND_ABX ||
                                                  last_instruction == AND_ABY ||
                                                  last_instruction == ORA_ABX ||
                                                  last_instruction == ORA_ABY ||
                                                  last_instruction == ADC_ABX ||
                                                  last_instruction == ADC_ABY ||
                                                  last_instruction == SBC_ABX ||
                                                  last_instruction == SBC_ABY ||
                                                  last_instruction == CMP_ABX ||
                                                  last_instruction == CMP_ABY ||
                                                  last_instruction == LDA_IDX ||
                                                  last_instruction == ORA_IDX ||
                                                  last_instruction == EOR_IDX ||
                                                  last_instruction == AND_IDX ||
                                                  last_instruction == ADC_IDX ||
                                                  last_instruction == CMP_IDX ||
                                                  last_instruction == SBC_IDX
                                                ) : {
                                                        if (alu_opcode != last_instruction) {
                                                                dut_error("alu_opcode is Wrong!");
                                                        };
                                                        if (alu_enable != 1) {
                                                                dut_error("alu_enable is Wrong!");
                                                        };
                                                        if (addr != PC) {
                                                                dut_error("Address is Wrong!");
                                                        };
                                                };
                                                --(
                                                --) : {
                                                --      if (alu_opcode != last_instruction) {
                                                --              dut_error("alu_opcode is Wrong!");
                                                --      };
                                                --      if (alu_enable != 1) {
                                                --              dut_error("alu_enable is Wrong!");
                                                --      };
                                                --      if (addr[7:0] != PCL) {
                                                --              dut_error("Address is Wrong!");
                                                --      };
                                                --      if (addr[12:8] != PCH[4:0]) {
                                                --              dut_error("Address is Wrong!");
                                                --      };
                                                --};
                                                default : {
                                                        if (alu_opcode.as_a(byte) != 0) {
                                                                dut_error("alu_opcode is Wrong!");
                                                        };
                                                        if (alu_enable != 0) {
                                                                dut_error("alu_enable is Wrong!");
                                                        };
                                                        if (alu_a != 0) {
                                                                dut_error("alu_a is Wrong!");
                                                        };
                                                        if (addr != PC) {
                                                                dut_error("Address is Wrong!");
                                                        };
                                                };
                                        };
                                }
                                else {
                                        rst = 0;
                                        if (alu_enable != 0) {
                                                dut_error("alu_enable is Wrong!");
                                        };
                                        if (alu_opcode.as_a(byte) != 0) {
                                                dut_error("alu_opcode is Wrong!");
                                        };
                                        if (alu_a != 0) {
                                                dut_error("alu_a is Wrong!");
                                        };
                                        if (addr != PC) {
                                                dut_error("Address is Wrong!");
                                        };
                                };
                                PC = PC + 1;
                        };
                        CYCLE_2 : {
                                print_state();
                                print addr;
                                if (addr != PC) {
                                        dut_error("ADDR should be equal PC!");
                                };
                                if (mem_rw != 0) {
                                        dut_error("MEM_RW should be 0 (READ)");
                                };
                                case {
                                        (
                                          instructions == ADC_ABS ||
                                          instructions == ADC_IMM ||
                                          instructions == AND_ABS ||
                                          instructions == AND_IMM ||
                                          instructions == ASL_ABS ||
                                          instructions == BIT_ABS ||
                                          instructions == BRK_IMP ||
                                          instructions == CMP_ABS ||
                                          instructions == CMP_IMM ||
                                          instructions == CPX_IMM ||
                                          instructions == CPY_IMM ||
                                          instructions == DEC_ABS ||
                                          instructions == EOR_ABS ||
                                          instructions == EOR_IMM ||
                                          instructions == INC_ABS ||
                                          instructions == JMP_ABS ||
                                          instructions == LDA_ABS ||
                                          instructions == LDA_IMM ||
                                          instructions == LDX_ABS ||
                                          instructions == LDX_IMM ||
                                          instructions == LDY_ABS ||
                                          instructions == LDY_IMM ||
                                          instructions == LSR_ABS ||
                                          instructions == ORA_ABS ||
                                          instructions == ORA_IMM ||
                                          instructions == ROL_ABS ||
                                          instructions == ROR_ABS ||
                                          instructions == SBC_ABS ||
                                          instructions == SBC_IMM ||
                                          instructions == LDA_ZPG ||
                                          instructions == LDX_ZPG ||
                                          instructions == LDY_ZPG ||
                                          instructions == EOR_ZPG ||
                                          instructions == AND_ZPG ||
                                          instructions == ORA_ZPG ||
                                          instructions == ADC_ZPG ||
                                          instructions == SBC_ZPG ||
                                          instructions == CMP_ZPG ||
                                          instructions == BIT_ZPG ||
                                          instructions == ASL_ZPG ||
                                          instructions == LSR_ZPG ||
                                          instructions == ROL_ZPG ||
                                          instructions == ROR_ZPG ||
                                          instructions == INC_ZPG ||
                                          instructions == DEC_ZPG ||
                                          instructions == LDA_ZPX ||
                                          instructions == LDX_ZPY ||
                                          instructions == LDY_ZPX ||
                                          instructions == EOR_ZPX ||
                                          instructions == AND_ZPX ||
                                          instructions == ORA_ZPX ||
                                          instructions == ADC_ZPX ||
                                          instructions == SBC_ZPX ||
                                          instructions == CMP_ZPX ||
                                          instructions == ASL_ZPX ||
                                          instructions == LSR_ZPX ||
                                          instructions == ROL_ZPX ||
                                          instructions == ROR_ZPX ||
                                          instructions == INC_ZPX ||
                                          instructions == DEC_ZPX ||
                                          instructions == STX_ZPY ||
                                          instructions == STY_ZPX ||
                                          instructions == STA_ZPX ||
                                          instructions == LDA_ABX ||
                                          instructions == LDA_ABY ||
                                          instructions == LDX_ABY ||
                                          instructions == LDY_ABX ||
                                          instructions == EOR_ABX ||
                                          instructions == EOR_ABY ||
                                          instructions == AND_ABX ||
                                          instructions == AND_ABY ||
                                          instructions == ORA_ABX ||
                                          instructions == ORA_ABY ||
                                          instructions == ADC_ABX ||
                                          instructions == ADC_ABY ||
                                          instructions == SBC_ABX ||
                                          instructions == SBC_ABY ||
                                          instructions == CMP_ABX ||
                                          instructions == CMP_ABY ||
                                          instructions == ASL_ABX ||
                                          instructions == LSR_ABX ||
                                          instructions == ROL_ABX ||
                                          instructions == ROR_ABX ||
                                          instructions == INC_ABX ||
                                          instructions == DEC_ABX ||
                                          instructions == LDA_IDX ||
                                          instructions == STA_IDX ||
                                          instructions == ORA_IDX ||
                                          instructions == EOR_IDX ||
                                          instructions == AND_IDX ||
                                          instructions == ADC_IDX ||
                                          instructions == CMP_IDX ||
                                          instructions == SBC_IDX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                PC = PC + 1;
                                        };
                                        -- TODO: STX and STY should not
                                        -- TODO: they dont need access to alu at any cycle
                                        -- TODO: because X and Y are available at alu_x and alu_y
                                        (
                                          instructions == STA_ABS ||
                                          instructions == STA_ZPG ||
                                          instructions == STX_ABS ||
                                          instructions == STY_ABS ||
                                          instructions == STX_ZPG ||
                                          instructions == STY_ZPG
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                PC = PC + 1;
                                        };
                                        (
                                          instructions == NOP_IMP ||
                                          instructions == PHP_IMP ||
                                          instructions == PLA_IMP ||
                                          instructions == PLP_IMP ||
                                          instructions == RTI_IMP ||
                                          instructions == RTS_IMP
 
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                        };
                                        (
                                          instructions == ASL_ACC ||
                                          instructions == CLC_IMP ||
                                          instructions == CLD_IMP ||
                                          instructions == CLI_IMP ||
                                          instructions == CLV_IMP ||
                                          instructions == DEX_IMP ||
                                          instructions == DEY_IMP ||
                                          instructions == INX_IMP ||
                                          instructions == INY_IMP ||
                                          instructions == LSR_ACC ||
                                          instructions == PHA_IMP ||
                                          instructions == ROL_ACC ||
                                          instructions == ROR_ACC ||
                                          instructions == SEC_IMP ||
                                          instructions == SED_IMP ||
                                          instructions == SEI_IMP ||
                                          instructions == TAX_IMP ||
                                          instructions == TAY_IMP ||
                                          instructions == TXA_IMP ||
                                          instructions == TYA_IMP
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                        };
                                        //JSR_ABS : {
                                        //      if (alu_opcode.as_a(byte) != 0) {
                                        //              dut_error("Opcode is Wrong!");
                                        //      };
                                        //      if (mem_rw != 0) {
                                        //              dut_error("MEM_RW should be 1 (WRITE)");
                                        //      };
                                        //      if (alu_enable != 0) {
                                        //              dut_error("JSR_IMP is Wrong!");
                                        //      };
                                        //      if (addr != PC) {
                                        //              dut_error("ADDR should be equal SP!");
                                        //      };
                                        //      PC = PC + 1;
                                        //};
                                        (
                                          instructions == TSX_IMP
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("TSX_IMP is Wrong!");
                                                };
                                                if (alu_a != SP) {
                                                        dut_error("TSX_IMP is Wrong!");
                                                };
                                        };
                                        (
                                          instructions == TXS_IMP
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("TXS_IMP is Wrong!");
                                                };
                                                SP = SP_aux;
                                        };
                                };
                        };
                        CYCLE_3 : {
                                print_state();
                                print addr;
                                case {
                                        (
                                          instructions == BRK_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (data_out[4:0] != PC[12:8] && data_out[7:5] != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP - 1;
                                        };
                                        //JSR_ABS : {
                                        //      if (alu_opcode.as_a(byte) != 0) {
                                        //              dut_error("Opcode is Wrong!");
                                        //      };
                                        //      if (mem_rw != 0) {
                                        //              dut_error("MEM_RW should be 1 (WRITE)");
                                        //      };
                                        //      if (alu_enable != 0) {
                                        //              dut_error("JSR_IMP is Wrong!");
                                        //      };
                                        //      if (addr != PC) {
                                        //              dut_error("ADDR should be equal PC!");
                                        //      };
                                        //};
                                        -- TODO: This is probably an error STA should not use ALU on the third cycle
                                        (
                                          instructions == STA_ZPX ||
                                          instructions == STX_ZPY ||
                                          instructions == STY_ZPX
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (addr != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == STA_ZPG ||
                                          instructions == STX_ZPG ||
                                          instructions == STY_ZPG
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (addr != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == JMP_ABS
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                PC[7:0] = PCL;
                                                PC[12:8] = PCH[4:0];
                                        };
                                        (
                                          instructions == LDA_ZPX ||
                                          instructions == LDX_ZPY ||
                                          instructions == LDY_ZPX ||
                                          instructions == EOR_ZPX ||
                                          instructions == AND_ZPX ||
                                          instructions == ORA_ZPX ||
                                          instructions == ADC_ZPX ||
                                          instructions == SBC_ZPX ||
                                          instructions == CMP_ZPX ||
                                          instructions == ASL_ZPX ||
                                          instructions == LSR_ZPX ||
                                          instructions == ROL_ZPX ||
                                          instructions == ROR_ZPX ||
                                          instructions == INC_ZPX ||
                                          instructions == DEC_ZPX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == LDA_IDX ||
                                          instructions == STA_IDX ||
                                          instructions == ORA_IDX ||
                                          instructions == EOR_IDX ||
                                          instructions == AND_IDX ||
                                          instructions == ADC_IDX ||
                                          instructions == CMP_IDX ||
                                          instructions == SBC_IDX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr != pointer) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == ADC_ABS ||
                                          instructions == AND_ABS ||
                                          instructions == ASL_ABS ||
                                          instructions == BIT_ABS ||
                                          instructions == CMP_ABS ||
                                          instructions == DEC_ABS ||
                                          instructions == EOR_ABS ||
                                          instructions == INC_ABS ||
                                          instructions == LDA_ABS ||
                                          instructions == LDX_ABS ||
                                          instructions == LDY_ABS ||
                                          instructions == LSR_ABS ||
                                          instructions == ORA_ABS ||
                                          instructions == ROL_ABS ||
                                          instructions == ROR_ABS ||
                                          instructions == SBC_ABS ||
                                          instructions == STA_ABS ||
                                          instructions == STX_ABS ||
                                          instructions == STY_ABS ||
                                          instructions == LDA_ABX ||
                                          instructions == LDY_ABX ||
                                          instructions == EOR_ABX ||
                                          instructions == AND_ABX ||
                                          instructions == ORA_ABX ||
                                          instructions == ADC_ABX ||
                                          instructions == SBC_ABX ||
                                          instructions == CMP_ABX ||
                                          instructions == ASL_ABX ||
                                          instructions == LSR_ABX ||
                                          instructions == ROL_ABX ||
                                          instructions == ROR_ABX ||
                                          instructions == INC_ABX ||
                                          instructions == DEC_ABX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (addr != PC) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                PC = PC + 1;
                                                if (PCL + X > 255) {
                                                        more_cycles = TRUE;
                                                };
                                        };
                                        (
                                          instructions == LDA_ABY ||
                                          instructions == LDX_ABY ||
                                          instructions == AND_ABY ||
                                          instructions == EOR_ABY ||
                                          instructions == ORA_ABY ||
                                          instructions == ADC_ABY ||
                                          instructions == SBC_ABY ||
                                          instructions == CMP_ABY
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (addr != PC) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                PC = PC + 1;
                                                if (PCL + Y > 255) {
                                                        more_cycles = TRUE;
                                                };
                                        };
                                        (
                                          instructions == LDA_ZPG ||
                                          instructions == LDX_ZPG ||
                                          instructions == LDY_ZPG ||
                                          instructions == EOR_ZPG ||
                                          instructions == AND_ZPG ||
                                          instructions == ORA_ZPG ||
                                          instructions == ADC_ZPG ||
                                          instructions == SBC_ZPG ||
                                          instructions == CMP_ZPG ||
                                          instructions == BIT_ZPG ||
                                          instructions == ASL_ZPG ||
                                          instructions == LSR_ZPG ||
                                          instructions == ROL_ZPG ||
                                          instructions == ROR_ZPG ||
                                          instructions == INC_ZPG ||
                                          instructions == DEC_ZPG
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (addr != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == PHA_IMP ||
                                          instructions == PHP_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_a != 0) {
                                                        dut_error("PHP_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP - 1;
                                                if (alu_enable != 0) {
                                                        dut_error("PHP_IMP is Wrong!");
                                                };
                                        };
                                        (
                                          instructions == PLA_IMP ||
                                          instructions == PLP_IMP ||
                                          instructions == RTI_IMP ||
                                          instructions == RTS_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("PLA_IMP is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (READ)");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP + 1;
                                        };
                                };
                        };
                        CYCLE_4 : {
                                print_state();
                                print addr;
                                case {
                                        (
                                          instructions == BRK_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (data_out != PC[7:0]) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP - 1;
                                        };
                                        //JSR_ABS : {
                                        //      if (alu_opcode.as_a(byte) != 0) {
                                        //              dut_error("Opcode is Wrong!");
                                        //      };
                                        //      if (mem_rw != 1) {
                                        //              dut_error("MEM_RW should be 1 (WRITE)");
                                        //      };
                                        //      if (alu_enable != 0) {
                                        //              dut_error("JSR_ABS is Wrong!");
                                        //      };
                                        //      if (data_out != PC[7:0]) {
                                        //              dut_error("JSR_ABS is Wrong!");
                                        //      };
                                        //      if (addr != SP + 256) {
                                        //              dut_error("ADDR should be equal SP!");
                                        //      };
                                        //      SP = SP - 1;
                                        //};
                                        (
                                          instructions == LDA_ZPX ||
                                          instructions == LDY_ZPX ||
                                          instructions == EOR_ZPX ||
                                          instructions == AND_ZPX ||
                                          instructions == ORA_ZPX ||
                                          instructions == ADC_ZPX ||
                                          instructions == SBC_ZPX ||
                                          instructions == CMP_ZPX ||
                                          instructions == ASL_ZPX ||
                                          instructions == LSR_ZPX ||
                                          instructions == ROL_ZPX ||
                                          instructions == ROR_ZPX ||
                                          instructions == INC_ZPX ||
                                          instructions == DEC_ZPX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                --TODO: Isn`t it suppose to have ADDRH == 0????
                                                if (PCL + X > 255) {
                                                        if (addr[7:0] != PCL + X - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + X) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == LDA_ABX ||
                                          instructions == LDY_ABX ||
                                          instructions == EOR_ABX ||
                                          instructions == AND_ABX ||
                                          instructions == ORA_ABX ||
                                          instructions == ADC_ABX ||
                                          instructions == SBC_ABX ||
                                          instructions == CMP_ABX ||
                                          instructions == ASL_ABX ||
                                          instructions == LSR_ABX ||
                                          instructions == ROL_ABX ||
                                          instructions == ROR_ABX ||
                                          instructions == INC_ABX ||
                                          instructions == DEC_ABX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (PCL + X > 255) {
                                                        more_cycles = TRUE;
                                                        if (addr[7:0] != PCL + X - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + X) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == LDA_IDX ||
                                          instructions == STA_IDX ||
                                          instructions == ORA_IDX ||
                                          instructions == EOR_IDX ||
                                          instructions == AND_IDX ||
                                          instructions == ADC_IDX ||
                                          instructions == CMP_IDX ||
                                          instructions == SBC_IDX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (pointer + X > 255) {
                                                        if (addr[7:0] != pointer + X - 256) {
                                                                dut_error("ADDR is wrong");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != pointer + X) {
                                                                dut_error("ADDR is wrong");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == LDX_ZPY ||
                                          instructions == LDA_ABY ||
                                          instructions == LDX_ABY ||
                                          instructions == EOR_ABY ||
                                          instructions == AND_ABY ||
                                          instructions == ORA_ABY ||
                                          instructions == ADC_ABY ||
                                          instructions == SBC_ABY ||
                                          instructions == CMP_ABY
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (PCL + Y > 255) {
                                                        more_cycles = TRUE;
                                                        if (addr[7:0] != PCL + Y - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + Y) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == ADC_ABS ||
                                          instructions == AND_ABS ||
                                          instructions == ASL_ABS ||
                                          instructions == BIT_ABS ||
                                          instructions == CMP_ABS ||
                                          instructions == DEC_ABS ||
                                          instructions == EOR_ABS ||
                                          instructions == INC_ABS ||
                                          instructions == LDA_ABS ||
                                          instructions == LDX_ABS ||
                                          instructions == LDY_ABS ||
                                          instructions == LSR_ABS ||
                                          instructions == ORA_ABS ||
                                          instructions == ROL_ABS ||
                                          instructions == ROR_ABS ||
                                          instructions == SBC_ABS
                                          ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                        };
                                        (
                                          instructions == STA_ABS ||
                                          instructions == STX_ABS ||
                                          instructions == STY_ABS
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                        };
                                        (
                                          instructions == ASL_ZPG ||
                                          instructions == LSR_ZPG ||
                                          instructions == ROL_ZPG ||
                                          instructions == ROR_ZPG ||
                                          instructions == INC_ZPG ||
                                          instructions == DEC_ZPG
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == STA_ZPX ||
                                          instructions == STY_ZPX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (PCL + X > 255) {
                                                        if (addr[7:0] != PCL + X - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + X) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == STX_ZPY
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (PCL + Y > 255) {
                                                        if (addr[7:0] != PCL + Y - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + Y) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == PLA_IMP ||
                                          instructions == PLP_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (READ)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("PLP_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == RTI_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("RTI_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP + 1;
                                        };
                                        (
                                          instructions == RTS_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("RTS_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP + 1;
                                                PC[7:0] = PCL;
                                        };
                                };
                        };
                        CYCLE_5 : {
                                print_state();
                                print addr;
                                case {
                                        (
                                          instructions == BRK_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP - 1;
                                        };
                                        //JSR_ABS : {
                                        //      if (alu_opcode.as_a(byte) != 0) {
                                        //              dut_error("Opcode is Wrong!");
                                        //      };
                                        //      if (mem_rw != 1) {
                                        //              dut_error("MEM_RW should be 1 (WRITE)");
                                        //      };
                                        //      if (alu_enable != 0) {
                                        //              dut_error("JSR_ABS is Wrong!");
                                        //      };
                                        //      if (data_out != PC[12:8]) {
                                        //              dut_error("JSR_ABS is Wrong!");
                                        //      };
                                        //      if (addr != SP + 256) {
                                        //              dut_error("ADDR should be equal SP!");
                                        //      };
                                        //      SP = SP - 1;
                                        //};
                                        (
                                          instructions == LDA_IDX ||
                                          instructions == STA_IDX ||
                                          instructions == ORA_IDX ||
                                          instructions == EOR_IDX ||
                                          instructions == AND_IDX ||
                                          instructions == ADC_IDX ||
                                          instructions == CMP_IDX ||
                                          instructions == SBC_IDX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (pointer + X + 1 > 255) {
                                                        if (addr[7:0] != pointer + X + 1 - 256) {
                                                                dut_error("ADDR is wrong");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != pointer + X + 1) {
                                                                dut_error("ADDR is wrong");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == RTI_IMP
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("RTI_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                SP = SP + 1;
                                                PC[7:0] = PCL;
                                        };
                                        (
                                          instructions == RTS_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("SEI_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                PC[12:8] = PCH[4:0];
                                        };
                                        (
                                          instructions == ASL_ZPG ||
                                          instructions == LSR_ZPG ||
                                          instructions == ROL_ZPG ||
                                          instructions == ROR_ZPG ||
                                          instructions == INC_ZPG ||
                                          instructions == DEC_ZPG
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == LDA_ABX ||
                                          instructions == LDY_ABX ||
                                          instructions == EOR_ABX ||
                                          instructions == AND_ABX ||
                                          instructions == ORA_ABX ||
                                          instructions == ADC_ABX ||
                                          instructions == SBC_ABX ||
                                          instructions == CMP_ABX ||
                                          (
                                                more_cycles == TRUE &&
                                                (
                                                  instructions == ASL_ABX ||
                                                  instructions == LSR_ABX ||
                                                  instructions == ROL_ABX ||
                                                  instructions == ROR_ABX ||
                                                  instructions == INC_ABX ||
                                                  instructions == DEC_ABX
                                                )
                                          )
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X - 256) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0] + 1) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          more_cycles == FALSE &&
                                          (
                                                  instructions == ASL_ABX ||
                                                  instructions == LSR_ABX ||
                                                  instructions == ROL_ABX ||
                                                  instructions == ROR_ABX ||
                                                  instructions == INC_ABX ||
                                                  instructions == DEC_ABX
                                          )
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                        (
                                          instructions == LDX_ZPY ||
                                          instructions == LDA_ABY ||
                                          instructions == LDX_ABY ||
                                          instructions == EOR_ABY ||
                                          instructions == AND_ABY ||
                                          instructions == ORA_ABY ||
                                          instructions == ADC_ABY ||
                                          instructions == SBC_ABY ||
                                          instructions == CMP_ABY
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + Y - 256) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0] + 1) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          instructions == ASL_ZPX ||
                                          instructions == LSR_ZPX ||
                                          instructions == ROL_ZPX ||
                                          instructions == ROR_ZPX ||
                                          instructions == INC_ZPX ||
                                          instructions == DEC_ZPX
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (PCL + X > 255) {
                                                        if (addr[7:0] != PCL + X - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + X) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          instructions == ASL_ABS ||
                                          instructions == DEC_ABS ||
                                          instructions == INC_ABS ||
                                          instructions == LSR_ABS ||
                                          instructions == ROL_ABS ||
                                          instructions == ROR_ABS
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                };
                        };
                        CYCLE_6 : {
                                print_state();
                                print addr;
                                case {
                                        (
                                          instructions == BRK_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr != 13'b1111111111110) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                PC[7:0] = PCL;
                                        };
                                        //JSR_ABS : {
                                        //      if (alu_opcode.as_a(byte) != 0) {
                                        //              dut_error("Opcode is Wrong!");
                                        //      };
                                        //      if (mem_rw != 0) {
                                        //              dut_error("MEM_RW should be 1 (WRITE)");
                                        //      };
                                        //      if (alu_enable != 0) {
                                        //              dut_error("JSR_ABS is Wrong!");
                                        //      };
                                        //      if (addr != PC) {
                                        //              dut_error("ADDR should be equal SP!");
                                        //      };
                                        //      PC [7:0] = PCL;
                                        //      PC[12:8] = PCH[4:0];
                                        //};
                                        (
                                          instructions == LDA_IDX ||
                                          instructions == ORA_IDX ||
                                          instructions == EOR_IDX ||
                                          instructions == AND_IDX ||
                                          instructions == ADC_IDX ||
                                          instructions == CMP_IDX ||
                                          instructions == SBC_IDX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR is wrong");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR is wrong");
                                                };
                                        };
                                        (
                                          instructions == STA_IDX ||
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR is wrong");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR is wrong");
                                                };
                                        };
                                        (
                                          instructions == RTI_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("RTI_IMP is Wrong!");
                                                };
                                                if (addr != SP + 256) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                PC[12:8] = PCH[4:0];
                                        };
                                        (
                                          instructions == RTS_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("RTI_IMP is Wrong!");
                                                };
                                                if (addr != PC) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                PC = PC + 1;
                                        };
                                        (
                                          instructions == ASL_ZPX ||
                                          instructions == LSR_ZPX ||
                                          instructions == ROL_ZPX ||
                                          instructions == ROR_ZPX ||
                                          instructions == INC_ZPX ||
                                          instructions == DEC_ZPX
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (PCL + X > 255) {
                                                        if (addr[7:0] != PCL + X - 256) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                }
                                                else {
                                                        if (addr[7:0] != PCL + X) {
                                                                dut_error("ADDR should be equal SP!");
                                                        };
                                                };
                                        };
                                        (
                                          more_cycles == TRUE &&
                                          (
                                                instructions == ASL_ABX ||
                                                instructions == LSR_ABX ||
                                                instructions == ROL_ABX ||
                                                instructions == ROR_ABX ||
                                                instructions == INC_ABX ||
                                                instructions == DEC_ABX
                                          )
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X - 256) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0] + 1) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          more_cycles == FALSE &&
                                          (
                                                instructions == ASL_ABX ||
                                                instructions == LSR_ABX ||
                                                instructions == ROL_ABX ||
                                                instructions == ROR_ABX ||
                                                instructions == INC_ABX ||
                                                instructions == DEC_ABX
                                          )
                                        ) : {
                                                if (alu_opcode != instructions) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 1) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          instructions == ASL_ABS ||
                                          instructions == DEC_ABS ||
                                          instructions == INC_ABS ||
                                          instructions == LSR_ABS ||
                                          instructions == ROL_ABS ||
                                          instructions == ROR_ABS
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr[7:0] != PCL) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR should be equal SP!");
                                                };
                                        };
                                };
                        };
                        CYCLE_7 : {
                                print_state();
                                print addr;
                                case {
                                        (
                                          more_cycles == TRUE &&
                                          (
                                                instructions == ASL_ABX ||
                                                instructions == LSR_ABX ||
                                                instructions == ROL_ABX ||
                                                instructions == ROR_ABX ||
                                                instructions == INC_ABX ||
                                                instructions == DEC_ABX
                                          )
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X - 256) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0] + 1) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          more_cycles == FALSE &&
                                          (
                                                instructions == ASL_ABX ||
                                                instructions == LSR_ABX ||
                                                instructions == ROL_ABX ||
                                                instructions == ROR_ABX ||
                                                instructions == INC_ABX ||
                                                instructions == DEC_ABX
                                          )
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("ASL_ACC is Wrong!");
                                                };
                                                if (mem_rw != 1) {
                                                        dut_error("MEM_RW should be 0 (WRITE)");
                                                };
                                                if (addr[7:0] != PCL + X) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                                if (addr[12:8] != PCH[4:0]) {
                                                        dut_error("ADDR is wrong!");
                                                };
                                        };
                                        (
                                          instructions == BRK_IMP
                                        ) : {
                                                if (alu_opcode.as_a(byte) != 0) {
                                                        dut_error("Opcode is Wrong!");
                                                };
                                                if (mem_rw != 0) {
                                                        dut_error("MEM_RW should be 1 (WRITE)");
                                                };
                                                if (alu_enable != 0) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                if (addr != 13'b1111111111111) {
                                                        dut_error("BRK_IMP is Wrong!");
                                                };
                                                PC[12:8] = PCH[4:0];
                                        };
                                };
                        };
                };
        old_state = new_state;
        };
};
'>
Line No.	Rev	Author	Line
1	206	creep	`<'`
2			`import fsm_components;`
3			`type state_t : [RESET, CYCLE_1, CYCLE_2, CYCLE_3, CYCLE_4, CYCLE_5, CYCLE_6, CYCLE_7];`
4			`unit fsm_chk_u {`
5			`!A : byte;`
6			`keep soft A == 0;`
7			`!X : byte;`
8			`keep soft X == 0;`
9			`!Y : byte;`
10			`keep soft Y == 0;`
11			`!PC : uint(bits : 13);`
12			`keep soft PC == 0;`
13			`// !SP : uint(bits : 9);`
14			`// keep soft SP == 9'b100000000;`
15			`!SP : byte;`
16			`keep soft SP == 0;`
17	214	creep	`!pointer : byte;`
18			`keep soft pointer == 0;`
19	206	creep
20	212	creep	`!more_cycles : bool;`
21			`keep soft more_cycles == FALSE;`
22	206	creep	`--!R : byte;`
23			`-- keep soft R == 0;`
24			`--!PS : byte;`
25			`-- keep soft PS[0:0] == 0;`
26			`-- keep soft PS[1:1] == 0;`
27			`-- keep soft PS[2:2] == 0;`
28			`-- keep soft PS[3:3] == 0;`
29			`-- keep soft PS[4:4] == 0;`
30			`-- keep soft PS[5:5] == 1;`
31			`-- keep soft PS[6:6] == 0;`
32			`-- keep soft PS[7:7] == 0;`
33			`-- N : bit;`
34			`-- V : bit;`
35			`-- B : bit;`
36			`-- D : bit;`
37			`-- I : bit;`
38			`-- Z : bit;`
39			`-- C : bit;`
40			`-- keep soft N == 0;`
41			`-- keep soft V == 0;`
42			`-- keep soft B == 0;`
43			`-- keep soft D == 0;`
44			`-- keep soft I == 0;`
45			`-- keep soft Z == 0;`
46			`-- keep soft C == 0;`
47
48			`!new_inst : bool;`
49			`keep new_inst == FALSE;`
50			`!new_input : fsm_input_s;`
51			`!old_input : fsm_input_s;`
52			`--!new_inst : bool;`
53			`--keep soft new_inst == FALSE;`
54
55			`--!i : ps_index;`
56
57			`!new_state : state_t;`
58			`!old_state : state_t;`
59
60			`--count_cycles : int;`
61			`--first_cycle : bool;`
62			`--last_a : byte;`
63			`--last_status : byte;`
64			`--last_result : byte;`
65			`!PCL:byte;`
66			`!PCH:byte;`
67			`!SP_aux:byte;`
68			`!rst : bit;`
69			`!rst_counter : byte;`
70
71			`--keep first_cycle == TRUE;`
72			`--keep count_cycles == 0;`
73			`keep rst_counter == 0;`
74
75			`!instruction : valid_opcodes;`
76			`!last_instruction : valid_opcodes;`
77			`!instructions : valid_opcodes;`
78
79			`print_state () is {`
80			`outf("-------------------------------------------------------\n");`
81			`print instructions;`
82			`-- print instruction;`
83			`print 't6507lp_fsm.ir';`
84			`print 't6507lp_fsm.sp';`
85			`print SP + 256;`
86			`print 't6507lp_fsm.pc';`
87			`print PC;`
88			`--print addr;`
89			`case ('t6507lp_fsm.state') {`
90
91			`2 : { outf(" t6507lp_fsm.state = FETCH_LOW\n");};`
92			`3 : { outf(" t6507lp_fsm.state = FETCH_HIGH\n"); };`
93			`4 : { outf(" t6507lp_fsm.state = READ_MEM\n"); };`
94			`5 : { outf(" t6507lp_fsm.state = DUMMY_WRT_CALC\n"); };`
95			`6 : { outf(" t6507lp_fsm.state = WRITE_MEM\n"); };`
96			`7 : { outf(" t6507lp_fsm.state = FETCH_OP_CALC_PARAM\n"); };`
97			`8 : { outf(" t6507lp_fsm.state = READ_MEM_CALC_INDEX\n"); };`
98			`9 : { outf(" t6507lp_fsm.state = FETCH_HIGH_CALC_INDEX\n"); };`
99			`10 : { outf(" t6507lp_fsm.state = READ_MEM_FIX_ADDR\n"); };`
100			`11 : { outf(" t6507lp_fsm.state = FETCH_OP_EVAL_BRANCH\n"); };`
101			`12 : { outf(" t6507lp_fsm.state = FETCH_OP_FIX_PC\n"); };`
102			`13 : { outf(" t6507lp_fsm.state = READ_FROM_POINTER\n"); };`
103			`14 : { outf(" t6507lp_fsm.state = READ_FROM_POINTER_X\n"); };`
104			`15 : { outf(" t6507lp_fsm.state = READ_FROM_POINTER_X1\n"); };`
105			`16 : { outf(" t6507lp_fsm.state = PUSH_PCH\n"); };`
106			`17 : { outf(" t6507lp_fsm.state = PUSH_PCL\n"); };`
107			`18 : { outf(" t6507lp_fsm.state = PUSH_STATUS\n"); };`
108			`19 : { outf(" t6507lp_fsm.state = FETCH_PCL\n"); };`
109			`20 : { outf(" t6507lp_fsm.state = FETCH_PCH\n"); };`
110			`21 : { outf(" t6507lp_fsm.state = INCREMENT_SP\n"); };`
111			`22 : { outf(" t6507lp_fsm.state = PULL_STATUS\n"); };`
112			`23 : { outf(" t6507lp_fsm.state = PULL_PCL\n"); };`
113			`24 : { outf(" t6507lp_fsm.state = PULL_PCH\n"); };`
114			`25 : { outf(" t6507lp_fsm.state = INCREMENT_PC\n"); };`
115			`26 : { outf(" t6507lp_fsm.state = PUSH_REGISTER\n"); };`
116			`27 : { outf(" t6507lp_fsm.state = PULL_REGISTER\n"); };`
117			`28 : { outf(" t6507lp_fsm.state = DUMMY\n"); };`
118			`31 : { outf(" t6507lp_fsm.state = RESET\n"); };`
119			`};`
120			`};`
121
122			`store(input : fsm_input_s) is {`
123			`--reset_n : bit;`
124			`--alu_result : byte;`
125			`--alu_status : byte;`
126			`--data_in : byte;`
127			`--alu_x : byte;`
128			`--alu_y : byte;`
129			`//print me;`
130			`//print input;`
131			`if (input.reset_n == 0) {`
132			`rst_counter = 0;`
133			`new_state = RESET;`
134			`old_state = RESET;`
135			`A = 0;`
136			`X = 0;`
137			`Y = 0;`
138			`PC = 0;`
139			`SP = 255;`
140			`}`
141			`else {`
142			`case (old_state) {`
143			`RESET : {`
144			`if (rst_counter == 7) {`
145			`new_state = CYCLE_1;`
146			`};`
147			`};`
148			`CYCLE_1 : {`
149			`instruction = input.data_in.as_a(valid_opcodes);`
150			`new_state = CYCLE_2;`
151			`};`
152			`CYCLE_2 : {`
153	212	creep	`X = input.alu_x;`
154			`Y = input.alu_y;`
155	206	creep	`case {`
156			`(`
157			`instruction == BRK_IMP \|\|`
158			`instruction == PHA_IMP \|\|`
159			`instruction == PHP_IMP \|\|`
160			`instruction == PLA_IMP \|\|`
161			`instruction == PLP_IMP \|\|`
162			`instruction == RTI_IMP \|\|`
163			`instruction == RTS_IMP`
164			`) : {`
165			`new_state = CYCLE_3;`
166			`};`
167			`//JSR_ABS : {`
168			`// new_state = CYCLE_3;`
169			`// PCL = input.data_in;`
170			`//};`
171			`(`
172			`instruction == ADC_ABS \|\|`
173			`instruction == ASL_ABS \|\|`
174			`instruction == BIT_ABS \|\|`
175			`instruction == AND_ABS \|\|`
176			`instruction == CMP_ABS \|\|`
177			`instruction == DEC_ABS \|\|`
178			`instruction == EOR_ABS \|\|`
179			`instruction == INC_ABS \|\|`
180			`instruction == JMP_ABS \|\|`
181			`instruction == LDA_ABS \|\|`
182			`instruction == LDX_ABS \|\|`
183			`instruction == LDY_ABS \|\|`
184			`instruction == LSR_ABS \|\|`
185			`instruction == ORA_ABS \|\|`
186			`instruction == ROL_ABS \|\|`
187			`instruction == ROR_ABS \|\|`
188			`instruction == SBC_ABS \|\|`
189			`instruction == STA_ABS \|\|`
190			`instruction == STX_ABS \|\|`
191			`instruction == STY_ABS \|\|`
192			`instruction == LDA_ZPG \|\|`
193			`instruction == LDX_ZPG \|\|`
194			`instruction == LDY_ZPG \|\|`
195			`instruction == EOR_ZPG \|\|`
196			`instruction == AND_ZPG \|\|`
197			`instruction == ORA_ZPG \|\|`
198			`instruction == ADC_ZPG \|\|`
199			`instruction == SBC_ZPG \|\|`
200			`instruction == CMP_ZPG \|\|`
201			`instruction == BIT_ZPG \|\|`
202			`instruction == STA_ZPG \|\|`
203			`instruction == STX_ZPG \|\|`
204			`instruction == STY_ZPG \|\|`
205			`instruction == ASL_ZPG \|\|`
206			`instruction == LSR_ZPG \|\|`
207			`instruction == ROL_ZPG \|\|`
208			`instruction == ROR_ZPG \|\|`
209			`instruction == INC_ZPG \|\|`
210	212	creep	`instruction == DEC_ZPG \|\|`
211	206	creep	`instruction == LDA_ZPX \|\|`
212			`instruction == LDX_ZPY \|\|`
213			`instruction == LDY_ZPX \|\|`
214			`instruction == EOR_ZPX \|\|`
215			`instruction == AND_ZPX \|\|`
216			`instruction == ORA_ZPX \|\|`
217			`instruction == ADC_ZPX \|\|`
218			`instruction == SBC_ZPX \|\|`
219	212	creep	`instruction == CMP_ZPX \|\|`
220			`instruction == ASL_ZPX \|\|`
221			`instruction == LSR_ZPX \|\|`
222			`instruction == ROL_ZPX \|\|`
223			`instruction == ROR_ZPX \|\|`
224			`instruction == INC_ZPX \|\|`
225			`instruction == DEC_ZPX \|\|`
226			`instruction == STA_ZPX \|\|`
227			`instruction == STX_ZPY \|\|`
228	214	creep	`instruction == STY_ZPX \|\|`
229	212	creep	`instruction == LDA_ABX \|\|`
230			`instruction == LDA_ABY \|\|`
231			`instruction == LDX_ABY \|\|`
232			`instruction == LDY_ABX \|\|`
233			`instruction == EOR_ABX \|\|`
234			`instruction == EOR_ABY \|\|`
235			`instruction == AND_ABX \|\|`
236			`instruction == AND_ABY \|\|`
237			`instruction == ORA_ABX \|\|`
238			`instruction == ORA_ABY \|\|`
239			`instruction == ADC_ABX \|\|`
240			`instruction == ADC_ABY \|\|`
241			`instruction == SBC_ABX \|\|`
242			`instruction == SBC_ABY \|\|`
243			`instruction == CMP_ABX \|\|`
244	214	creep	`instruction == CMP_ABY \|\|`
245			`instruction == ASL_ABX \|\|`
246			`instruction == LSR_ABX \|\|`
247			`instruction == ROL_ABX \|\|`
248			`instruction == ROR_ABX \|\|`
249			`instruction == INC_ABX \|\|`
250			`instruction == DEC_ABX`
251	212	creep	`) : {`
252			`new_state = CYCLE_3;`
253			`PCL = input.data_in;`
254			`};`
255			`(`
256	214	creep	`instruction == LDA_IDX \|\|`
257			`instruction == STA_IDX \|\|`
258			`instruction == ORA_IDX \|\|`
259			`instruction == EOR_IDX \|\|`
260			`instruction == AND_IDX \|\|`
261			`instruction == ADC_IDX \|\|`
262			`instruction == CMP_IDX \|\|`
263			`instruction == SBC_IDX`
264			`) : {`
265			`new_state = CYCLE_3;`
266			`pointer = input.data_in;`
267			`};`
268			`(`
269	206	creep	`instruction == TXS_IMP`
270			`) : {`
271			`new_state = CYCLE_1;`
272			`SP_aux = input.alu_x;`
273			`};`
274			`default : {`
275			`new_state = CYCLE_1;`
276			`};`
277			`};`
278			`};`
279			`CYCLE_3 : {`
280			`case {`
281	214	creep	`//JSR_ABS : {`
282			`// new_state = CYCLE_4;`
283			`// PCH = input.data_in;`
284			`//};`
285	206	creep	`(`
286			`instruction == BRK_IMP \|\|`
287			`instruction == PLA_IMP \|\|`
288			`instruction == PLP_IMP \|\|`
289			`instruction == RTI_IMP \|\|`
290			`instruction == RTS_IMP \|\|`
291			`instruction == ASL_ZPG \|\|`
292			`instruction == LSR_ZPG \|\|`
293			`instruction == ROL_ZPG \|\|`
294			`instruction == ROR_ZPG \|\|`
295			`instruction == INC_ZPG \|\|`
296	214	creep	`instruction == DEC_ZPG \|\|`
297	206	creep	`instruction == LDA_ZPX \|\|`
298			`instruction == LDX_ZPY \|\|`
299			`instruction == LDY_ZPX \|\|`
300			`instruction == EOR_ZPX \|\|`
301			`instruction == AND_ZPX \|\|`
302			`instruction == ORA_ZPX \|\|`
303			`instruction == ADC_ZPX \|\|`
304			`instruction == SBC_ZPX \|\|`
305	212	creep	`instruction == CMP_ZPX \|\|`
306			`instruction == ASL_ZPX \|\|`
307			`instruction == LSR_ZPX \|\|`
308			`instruction == ROL_ZPX \|\|`
309			`instruction == ROR_ZPX \|\|`
310			`instruction == INC_ZPX \|\|`
311			`instruction == DEC_ZPX \|\|`
312			`instruction == STA_ZPX \|\|`
313			`instruction == STX_ZPY \|\|`
314	214	creep	`instruction == STY_ZPX \|\|`
315			`instruction == LDA_IDX \|\|`
316			`instruction == STA_IDX \|\|`
317			`instruction == ORA_IDX \|\|`
318			`instruction == EOR_IDX \|\|`
319			`instruction == AND_IDX \|\|`
320			`instruction == ADC_IDX \|\|`
321			`instruction == CMP_IDX \|\|`
322			`instruction == SBC_IDX`
323	206	creep	`) : {`
324			`new_state = CYCLE_4;`
325			`};`
326			`(`
327			`instruction == ADC_ABS \|\|`
328			`instruction == ASL_ABS \|\|`
329			`instruction == BIT_ABS \|\|`
330			`instruction == AND_ABS \|\|`
331			`instruction == CMP_ABS \|\|`
332			`instruction == DEC_ABS \|\|`
333			`instruction == EOR_ABS \|\|`
334			`instruction == INC_ABS \|\|`
335			`instruction == LDA_ABS \|\|`
336			`instruction == LDX_ABS \|\|`
337			`instruction == LDY_ABS \|\|`
338			`instruction == LSR_ABS \|\|`
339			`instruction == ORA_ABS \|\|`
340			`instruction == ROL_ABS \|\|`
341			`instruction == ROR_ABS \|\|`
342			`instruction == SBC_ABS \|\|`
343			`instruction == STA_ABS \|\|`
344			`instruction == STX_ABS \|\|`
345	212	creep	`instruction == STY_ABS \|\|`
346			`instruction == LDA_ABX \|\|`
347			`instruction == LDA_ABY \|\|`
348			`instruction == LDX_ABY \|\|`
349			`instruction == LDY_ABX \|\|`
350			`instruction == EOR_ABX \|\|`
351			`instruction == EOR_ABY \|\|`
352			`instruction == AND_ABX \|\|`
353			`instruction == AND_ABY \|\|`
354			`instruction == ORA_ABX \|\|`
355			`instruction == ORA_ABY \|\|`
356			`instruction == ADC_ABX \|\|`
357			`instruction == ADC_ABY \|\|`
358			`instruction == SBC_ABX \|\|`
359			`instruction == SBC_ABY \|\|`
360			`instruction == CMP_ABX \|\|`
361	214	creep	`instruction == CMP_ABY \|\|`
362			`instruction == ASL_ABX \|\|`
363			`instruction == LSR_ABX \|\|`
364			`instruction == ROL_ABX \|\|`
365			`instruction == ROR_ABX \|\|`
366			`instruction == INC_ABX \|\|`
367			`instruction == DEC_ABX`
368	206	creep	`) : {`
369			`new_state = CYCLE_4;`
370			`PCH = input.data_in;`
371			`};`
372			`(`
373			`instruction == JMP_ABS`
374			`) : {`
375			`new_state = CYCLE_1;`
376			`PCH = input.data_in;`
377			`};`
378			`default : {`
379			`new_state = CYCLE_1;`
380			`};`
381			`};`
382			`};`
383			`CYCLE_4 : {`
384			`case {`
385			`//JSR_ABS : {`
386			`// new_state = CYCLE_5;`
387			`//};`
388			`(`
389			`instruction == RTS_IMP`
390			`) : {`
391			`new_state = CYCLE_5;`
392			`PCL = input.data_in;`
393			`};`
394			`(`
395			`instruction == ASL_ABS \|\|`
396			`instruction == BRK_IMP \|\|`
397			`instruction == DEC_ABS \|\|`
398			`instruction == INC_ABS \|\|`
399			`instruction == LSR_ABS \|\|`
400			`instruction == ROL_ABS \|\|`
401			`instruction == ROR_ABS \|\|`
402			`instruction == RTI_IMP \|\|`
403			`instruction == ASL_ZPG \|\|`
404			`instruction == LSR_ZPG \|\|`
405			`instruction == ROL_ZPG \|\|`
406			`instruction == ROR_ZPG \|\|`
407			`instruction == INC_ZPG \|\|`
408	212	creep	`instruction == DEC_ZPG \|\|`
409			`instruction == ASL_ZPX \|\|`
410			`instruction == LSR_ZPX \|\|`
411			`instruction == ROL_ZPX \|\|`
412			`instruction == ROR_ZPX \|\|`
413			`instruction == INC_ZPX \|\|`
414			`instruction == DEC_ZPX \|\|`
415	214	creep	`instruction == ASL_ABX \|\|`
416			`instruction == LSR_ABX \|\|`
417			`instruction == ROL_ABX \|\|`
418			`instruction == ROR_ABX \|\|`
419			`instruction == INC_ABX \|\|`
420			`instruction == DEC_ABX \|\|`
421	212	creep	`(`
422			`more_cycles == TRUE &&`
423			`(`
424			`instruction == LDA_ABX \|\|`
425			`instruction == LDA_ABY \|\|`
426			`instruction == LDX_ABY \|\|`
427			`instruction == LDY_ABX \|\|`
428			`instruction == EOR_ABX \|\|`
429			`instruction == EOR_ABY \|\|`
430			`instruction == AND_ABX \|\|`
431			`instruction == AND_ABY \|\|`
432			`instruction == ORA_ABX \|\|`
433			`instruction == ORA_ABY \|\|`
434			`instruction == ADC_ABX \|\|`
435			`instruction == ADC_ABY \|\|`
436			`instruction == SBC_ABX \|\|`
437			`instruction == SBC_ABY \|\|`
438			`instruction == CMP_ABX \|\|`
439			`instruction == CMP_ABY`
440			`)`
441			`)`
442	206	creep	`) : {`
443			`new_state = CYCLE_5;`
444			`};`
445	214	creep	`(`
446			`instruction == LDA_IDX \|\|`
447			`instruction == STA_IDX \|\|`
448			`instruction == ORA_IDX \|\|`
449			`instruction == EOR_IDX \|\|`
450			`instruction == AND_IDX \|\|`
451			`instruction == ADC_IDX \|\|`
452			`instruction == CMP_IDX \|\|`
453			`instruction == SBC_IDX`
454			`) : {`
455			`new_state = CYCLE_5;`
456			`PCL = input.data_in;`
457			`};`
458	206	creep	`default : {`
459			`new_state = CYCLE_1;`
460			`};`
461			`};`
462			`};`
463			`CYCLE_5 : {`
464			`case {`
465			`//JSR_ABS : {`
466			`// new_state = CYCLE_6;`
467			`//};`
468			`(`
469			`instruction == RTI_IMP`
470			`) : {`
471			`new_state = CYCLE_6;`
472			`PCL = input.data_in;`
473			`};`
474			`(`
475			`instruction == RTS_IMP`
476			`) : {`
477			`new_state = CYCLE_6;`
478			`PCH = input.data_in;`
479			`};`
480			`(`
481			`instruction == ASL_ABS \|\|`
482			`instruction == BRK_IMP \|\|`
483			`instruction == DEC_ABS \|\|`
484			`instruction == INC_ABS \|\|`
485			`instruction == LSR_ABS \|\|`
486			`instruction == ROL_ABS \|\|`
487	212	creep	`instruction == ROR_ABS \|\|`
488			`instruction == ASL_ZPX \|\|`
489			`instruction == LSR_ZPX \|\|`
490			`instruction == ROL_ZPX \|\|`
491			`instruction == ROR_ZPX \|\|`
492			`instruction == INC_ZPX \|\|`
493	214	creep	`instruction == DEC_ZPX \|\|`
494			`instruction == ASL_ABX \|\|`
495			`instruction == LSR_ABX \|\|`
496			`instruction == ROL_ABX \|\|`
497			`instruction == ROR_ABX \|\|`
498			`instruction == INC_ABX \|\|`
499			`instruction == DEC_ABX`
500	206	creep	`) : {`
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