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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Blame information for rev 232

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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// t2600 IP Core                                                      ////
////                                                                    ////
//// This file is part of the t2600 project                             ////
//// http://www.opencores.org/cores/t2600/                              ////
////                                                                    ////
//// Description                                                        ////
//// VGA controller                                                     ////
////                                                                    ////
//// TODO:                                                              ////
//// - Feed the controller with data                                    ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter, clk_358);
 
input reset_n;
input clk_50;
output reg [11:0] pixel;
output reg [8:0] vert_counter;
output reg [7:0] hor_counter;
 
output reg clk_358; // 3.58mhz
reg [3:0] counter;
 
reg [3:0] red;
reg [3:0] green;
reg [3:0] blue;
 
always @ (posedge clk_50 or negedge reset_n) begin
        if (reset_n == 1'b0) begin
                clk_358 <= 1'b0;
                counter <= 4'd0;
                red <= 4'b1010;
                green <= 4'b0001;
                blue <= 4'b1110;
        end
        else begin
                red <= 4'b1010;
                green <= 4'b0001;
                blue <= 4'b1110;
 
                if (counter == 4'h6) begin
                        clk_358 <= !clk_358;
                        counter <= 4'd0;
                end
                else begin
                        counter <= counter + 4'd1;
                end
        end
end
 
always @ (posedge clk_358 or negedge reset_n) begin
        if (reset_n == 1'b0) begin
                hor_counter <= 8'd0;
                vert_counter <= 9'd0;
        end
        else begin
                if (hor_counter == 8'd227) begin // last colum
                        hor_counter <= 8'd0;
 
                        if (vert_counter == 9'd261) begin // last line
                                vert_counter <= 9'd0;
                        end
                        else begin
                                vert_counter <= vert_counter + 9'd1;
                        end
                end
                else begin
                        hor_counter <= hor_counter + 8'd1;
                end
        end
end
 
always @(*) begin // comb logic
        if (hor_counter < 10) begin
                pixel = {red, green, blue};
        end
        else begin
                pixel = {red, red, green};
        end
end
 
endmodule

Line No.	Rev	Author	Line
1	222	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// t2600 IP Core ////`
4			`//// ////`
5			`//// This file is part of the t2600 project ////`
6			`//// http://www.opencores.org/cores/t2600/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// VGA controller ////`
10			`//// ////`
11			`//// TODO: ////`
12			`//// - Feed the controller with data ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47	232	creep	`module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter, clk_358);`
48	222	creep
49	227	creep	`input reset_n;`
50	225	gabrielosh	`input clk_50;`
51	230	creep	`output reg [11:0] pixel;`
52			`output reg [8:0] vert_counter;`
53			`output reg [7:0] hor_counter;`
54	222	creep
55	232	creep	`output reg clk_358; // 3.58mhz`
56	222	creep	`reg [3:0] counter;`
57
58			`reg [3:0] red;`
59			`reg [3:0] green;`
60			`reg [3:0] blue;`
61
62	227	creep	`always @ (posedge clk_50 or negedge reset_n) begin`
63			`if (reset_n == 1'b0) begin`
64	222	creep	`clk_358 <= 1'b0;`
65			`counter <= 4'd0;`
66			`red <= 4'b1010;`
67			`green <= 4'b0001;`
68			`blue <= 4'b1110;`
69			`end`
70			`else begin`
71	230	creep	`red <= 4'b1010;`
72			`green <= 4'b0001;`
73			`blue <= 4'b1110;`
74
75	222	creep	`if (counter == 4'h6) begin`
76			`clk_358 <= !clk_358;`
77			`counter <= 4'd0;`
78			`end`
79			`else begin`
80	227	creep	`counter <= counter + 4'd1;`
81	222	creep	`end`
82	227	creep	`end`
83	222	creep	`end`
84
85	227	creep	`always @ (posedge clk_358 or negedge reset_n) begin`
86			`if (reset_n == 1'b0) begin`
87	230	creep	`hor_counter <= 8'd0;`
88	231	gabrielosh	`vert_counter <= 9'd0;`
89	222	creep	`end`
90			`else begin`
91	230	creep	`if (hor_counter == 8'd227) begin // last colum`
92			`hor_counter <= 8'd0;`
93	222	creep
94	230	creep	`if (vert_counter == 9'd261) begin // last line`
95			`vert_counter <= 9'd0;`
96			`end`
97			`else begin`
98			`vert_counter <= vert_counter + 9'd1;`
99			`end`
100	222	creep	`end`
101			`else begin`
102	230	creep	`hor_counter <= hor_counter + 8'd1;`
103	222	creep	`end`
104			`end`
105	227	creep	`end`
106	222	creep
107	230	creep	`always @(*) begin // comb logic`
108	232	creep	`if (hor_counter < 10) begin`
109			`pixel = {red, green, blue};`
110			`end`
111			`else begin`
112			`pixel = {red, red, green};`
113			`end`
114	222	creep	`end`
115
116			`endmodule`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Blame information for rev 232