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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 146

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////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// T6507LP IP Core                                                    ////
////                                                                    ////
//// This file is part of the T6507LP project                           ////
//// http://www.opencores.org/cores/t6507lp/                            ////
////                                                                    ////
//// Description                                                        ////
//// 6507 ALU                                                           ////
////                                                                    ////
//// To Do:                                                             ////
//// - Search for TODO                                                  ////
////                                                                    ////
//// Author(s):                                                         ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
////                                                                    ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                       ////
////                                                                    ////
//// This source file may be used and distributed without               ////
//// restriction provided that this copyright statement is not          ////
//// removed from the file and that any derivative work contains        ////
//// the original copyright notice and the associated disclaimer.       ////
////                                                                    ////
//// This source file is free software; you can redistribute it         ////
//// and/or modify it under the terms of the GNU Lesser General         ////
//// Public License as published by the Free Software Foundation;       ////
//// either version 2.1 of the License, or (at your option) any         ////
//// later version.                                                     ////
////                                                                    ////
//// This source is distributed in the hope that it will be             ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
//// PURPOSE. See the GNU Lesser General Public License for more        ////
//// details.                                                           ////
////                                                                    ////
//// You should have received a copy of the GNU Lesser General          ////
//// Public License along with this source; if not, download it         ////
//// from http://www.opencores.org/lgpl.shtml                           ////
////                                                                    ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// TODO: verify code identation
 
module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
 
input wire       clk;
input wire       reset_n;
input wire       alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
reg [7:0] bcd1;
reg [7:0] bcd2;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
        if (reset_n == 0) begin
                //$display("RESTART");
                alu_result <= 0;
                alu_status[C] <= 0;
                alu_status[N] <= 0;
                alu_status[V] <= 0;
                alu_status[Z] <= 1;
                alu_status[I] <= 0;
                alu_status[B] <= 0;
                alu_status[D] <= 0;
                A <= 0;
                X <= 0;
                Y <= 0;
                alu_x <= 0;
                alu_y <= 0;
        end
        else if ( alu_enable == 1 ) begin
                case (alu_opcode)
                        ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
                        AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
                        ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
                        EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
                        ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
                        SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
                        LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :
                        begin
                                A          <= result;
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
                        begin
                                X          <= result;
                                alu_x      <= result;
                                alu_status <= STATUS;
                        end
                        TXS_IMP :
                        begin
                                X     <= result;
                                alu_x <= result;
                        end
                        LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
                        begin
                                Y          <= result;
                                alu_y      <= result;
                                alu_status <= STATUS;
                        end
                        LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,
                        ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS,
                        CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,
                        CPY_ZPG, CPY_ABS, PHP_IMP :
                        begin
                                alu_status <= STATUS;
                        end
                        SEC_IMP :
                        begin
                                alu_status[C] <= 1;
                        end
                        SED_IMP :
                        begin
                                alu_status[D] <= 1;
                        end
                        SEI_IMP :
                        begin
                                alu_status[I] <= 1;
                        end
                        CLC_IMP :
                        begin
                                alu_status[C] <= 0;
                        end
                        CLD_IMP :
                        begin
                                alu_status[D] <= 0;
                        end
                        CLI_IMP :
                        begin
                                alu_status[I] <= 0;
                        end
                        CLV_IMP :
                        begin
                                alu_status[V] <= 0;
                        end
                        BRK_IMP :
                        begin
                                alu_status[B] <= 0;
                        end
                        PLP_IMP, RTI_IMP :
                        begin
                                alu_status <= alu_a;
                        end
                        BIT_ZPG, BIT_ABS :
                        begin
                                alu_status[Z] <= STATUS[Z];
                                alu_status[V] <= alu_a[6];
                                alu_status[N] <= alu_a[7];
                        end
                        INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :
                        begin
                                alu_result <= result;
                                alu_status <= STATUS;
                        end
                        default : begin
                                //$display("ERROR");
                        end
                endcase
        end
end
 
always @ (*) begin
        bcd1      = A;
        bcd2      = alu_a;
        result    = alu_result;
        STATUS[C] = alu_status[C];
        STATUS[V] = alu_status[V];
        STATUS[5] = 1;
        STATUS[B] = alu_status[B];
        STATUS[I] = alu_status[I];
        STATUS[D] = alu_status[D];
 
        case (alu_opcode)
                // BIT - Bit Test
                BIT_ZPG, BIT_ABS: begin
                        result = A & alu_a;
                end
 
                // BRK - Force Interrupt
                BRK_IMP: begin
                        STATUS[B] = 1'b1;
                end
 
                // CLC - Clear Carry Flag
                CLC_IMP: begin
                        STATUS[C] = 1'b0;
                end
 
                // CLD - Clear Decimal Flag
                CLD_IMP: begin
                        STATUS[D] = 1'b0;
                end
 
                // CLI - Clear Interrupt Disable
                // TODO: verify if this should be supported by 6507
                CLI_IMP: begin
                        STATUS[I] = 1'b0;
                end
 
                // CLV - Clear Overflow Flag
                CLV_IMP: begin
                        STATUS[V] = 1'b0;
                end
 
                // NOP - No Operation
                //NOP_IMP: begin
                        // Do nothing :-D
                //end
 
                // PLP - Pull Processor Status Register
                PLP_IMP, RTI_IMP: begin
                        STATUS = alu_a;
                end
 
                // STA - Store Accumulator
                // PHA - Push A
                // TAX - Transfer Accumulator to X
                // TAY - Transfer Accumulator to Y
                TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
                        result = A;
                end
 
                // STX - Store X Register
                // TXA - Transfer X to Accumulator
                // TXS - Transfer X to Stack pointer
                STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
                        result = X;
                end
 
                // STY - Store Y Register
                // TYA - Transfer Y to Accumulator
                STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
                        result = Y;
                end
 
                // SEC - Set Carry Flag
                SEC_IMP: begin
                        STATUS[C] = 1'b1;
                end
 
                // SED - Set Decimal Flag
                SED_IMP: begin
                        STATUS[D] = 1'b1;
                end
 
                // SEI - Set Interrupt Disable
                SEI_IMP: begin
                        STATUS[I] = 1'b1;
                end
 
                // INC - Increment memory
                INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
                        result = alu_a + 1;
                end
 
                // INX - Increment X Register
                INX_IMP: begin
                        result = X + 1;
                end
 
                // INY - Increment Y Register
                INY_IMP : begin
                        result = Y + 1;
                end
 
                // DEC - Decrement memory
                DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
                        result = alu_a - 1;
                end
 
                // DEX - Decrement X register
                DEX_IMP: begin
                        result = X - 1;
                end
 
                // DEY - Decrement Y Register
                DEY_IMP: begin
                        result = Y - 1;
                end
 
                // ADC - Add with carry
                ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        bcd1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (bcd1[7:4] > 9) begin
                                        bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        bcd2 = alu_a + 6;
                                end
                                if (bcd2[7:4] > 9) begin
                                        bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
 
                        {STATUS[C],result} = bcd1 + bcd2 + alu_status[C];
                        if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
 
                        if (alu_status[D] == 1) begin
                                if (result[3:0] > 9) begin
                                        result = result[3:0] + 6; // A = A - 10 and A = A + 16
                                end
                                if (result[7:4] > 9) begin
                                        result = result[7:4] + 6; // A = A - 10 and A = A + 16
                                        STATUS[C] = 1;
                                end
                        end
                end
 
                // AND - Logical AND
                AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
                        result = A & alu_a;
                end
 
                // CMP - Compare
                CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
                        result = A - alu_a;
                        STATUS[C] = (A >= alu_a) ? 1 : 0;
                end
 
                // EOR - Exclusive OR
                EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
                        result = A ^ alu_a ;
                end
 
                // LDA - Load Accumulator
                // LDX - Load X Register
                // LDY - Load Y Register
                // TSX - Transfer Stack Pointer to X
                LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
                LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
                LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
                TSX_IMP : begin
                        result = alu_a;
                end
 
                // ORA - Logical OR
                ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
                        result = A | alu_a;
                end
 
                // SBC - Subtract with Carry
                SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
                        if (alu_status[D] == 1) begin
                                if (A[3:0] > 9) begin
                                        bcd1 = A + 6; // A = A - 10 and A = A + 16
                                end
                                if (bcd1[7:4] > 9) begin
                                        bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                                if (alu_a[3:0] > 9) begin
                                        bcd2 = alu_a + 6;
                                end
                                if (bcd2[7:4] > 9) begin
                                        bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16
                                end
                        end
 
                        {STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];
                        if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))
                                STATUS[V] = 1;
                        else
                                STATUS[V] = 0;
                end
 
                // ASL - Arithmetic Shift Left
                ASL_ACC : begin
                        //{STATUS[C],result} = A << 1;
                        {STATUS[C],result} = {A,1'b0};
                end
                ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
                        //{STATUS[C],result} = alu_a << 1;
                        {STATUS[C],result} = {alu_a,1'b0};
                end
 
                // LSR - Logical Shift Right
                LSR_ACC: begin
                        //{result, STATUS[C]} = A >> 1;
                        {result,STATUS[C]} = {1'b0,A};
                end
                LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
                        //{result, STATUS[C]} = alu_a >> 1;
                        {result,STATUS[C]} = {1'b0,alu_a};
                end
 
                // ROL - Rotate Left
                ROL_ACC : begin
                        {STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?
                end
                ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
                        {STATUS[C],result} = {alu_a,alu_status[C]};
                end
 
                // ROR - Rotate Right           
                ROR_ACC : begin
                        {result,STATUS[C]} = {alu_status[C],A};
                end
                ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
                        {result, STATUS[C]} = {alu_status[C], alu_a};
                end
 
                // CPX - Compare X Register
                CPX_IMM, CPX_ZPG, CPX_ABS : begin
                        result = X - alu_a;
                        STATUS[C] = (X >= alu_a) ? 1 : 0;
                end
 
                // CPY - Compare Y Register
                CPY_IMM, CPY_ZPG, CPY_ABS : begin
                        result = Y - alu_a;
                        STATUS[C] = (Y >= alu_a) ? 1 : 0;
                end
 
                default: begin // NON-DEFAULT OPCODES FALL HERE
                end
        endcase
        STATUS[Z] = (result == 0) ? 1 : 0;
        STATUS[N] = result[7];
end
 
endmodule
 

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Blame information for rev 146

Line No.	Rev	Author	Line
1	141	creep	`////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// T6507LP IP Core ////`
4			`//// ////`
5			`//// This file is part of the T6507LP project ////`
6			`//// http://www.opencores.org/cores/t6507lp/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 6507 ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - Search for TODO ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
16			`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
17			`//// ////`
18			`////////////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`////////////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`// TODO: verify code identation`
48
49			`module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );`
50
51			`input wire clk;`
52			`input wire reset_n;`
53			`input wire alu_enable;`
54			`input wire [7:0] alu_opcode;`
55			`input wire [7:0] alu_a;`
56			`output reg [7:0] alu_result;`
57			`output reg [7:0] alu_status;`
58			`output reg [7:0] alu_x;`
59			`output reg [7:0] alu_y;`
60
61			`reg [7:0] A;`
62			`reg [7:0] X;`
63			`reg [7:0] Y;`
64
65			`reg [7:0] STATUS;`
66			`reg [7:0] result;`
67			`reg [7:0] bcd1;`
68			`reg [7:0] bcd2;`
69
70			`include "t6507lp_package.v"
71
72			`always @ (posedge clk or negedge reset_n)`
73			`begin`
74			`if (reset_n == 0) begin`
75			`//$display("RESTART");`
76			`alu_result <= 0;`
77			`alu_status[C] <= 0;`
78			`alu_status[N] <= 0;`
79			`alu_status[V] <= 0;`
80			`alu_status[Z] <= 1;`
81			`alu_status[I] <= 0;`
82			`alu_status[B] <= 0;`
83			`alu_status[D] <= 0;`
84			`A <= 0;`
85			`X <= 0;`
86			`Y <= 0;`
87			`alu_x <= 0;`
88			`alu_y <= 0;`
89			`end`
90			`else if ( alu_enable == 1 ) begin`
91			`case (alu_opcode)`
92			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,`
93			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,`
94			`ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,`
95			`EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,`
96			`ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,`
97			`SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,`
98			`LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP, TXA_IMP, TYA_IMP :`
99			`begin`
100			`A <= result;`
101			`alu_result <= result;`
102			`alu_status <= STATUS;`
103			`end`
104			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :`
105			`begin`
106			`X <= result;`
107			`alu_x <= result;`
108			`alu_status <= STATUS;`
109			`end`
110			`TXS_IMP :`
111			`begin`
112			`X <= result;`
113			`alu_x <= result;`
114			`end`
115			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :`
116			`begin`
117			`Y <= result;`
118			`alu_y <= result;`
119			`alu_status <= STATUS;`
120			`end`
121			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX, ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX,`
122			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX, CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS,`
123			`CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY, CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM,`
124			`CPY_ZPG, CPY_ABS, PHP_IMP :`
125			`begin`
126			`alu_status <= STATUS;`
127			`end`
128			`SEC_IMP :`
129			`begin`
130			`alu_status[C] <= 1;`
131			`end`
132			`SED_IMP :`
133			`begin`
134			`alu_status[D] <= 1;`
135			`end`
136			`SEI_IMP :`
137			`begin`
138			`alu_status[I] <= 1;`
139			`end`
140			`CLC_IMP :`
141			`begin`
142			`alu_status[C] <= 0;`
143			`end`
144			`CLD_IMP :`
145			`begin`
146			`alu_status[D] <= 0;`
147			`end`
148			`CLI_IMP :`
149			`begin`
150			`alu_status[I] <= 0;`
151			`end`
152			`CLV_IMP :`
153			`begin`
154			`alu_status[V] <= 0;`
155			`end`
156			`BRK_IMP :`
157			`begin`
158			`alu_status[B] <= 0;`
159			`end`
160			`PLP_IMP, RTI_IMP :`
161			`begin`
162			`alu_status <= alu_a;`
163			`end`
164			`BIT_ZPG, BIT_ABS :`
165			`begin`
166			`alu_status[Z] <= STATUS[Z];`
167			`alu_status[V] <= alu_a[6];`
168			`alu_status[N] <= alu_a[7];`
169			`end`
170	145	gabrielosh	`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :`
171	141	creep	`begin`
172			`alu_result <= result;`
173			`alu_status <= STATUS;`
174			`end`
175			`default : begin`
176			`//$display("ERROR");`
177			`end`
178			`endcase`
179			`end`
180			`end`
181
182			`always @ (*) begin`
183			`bcd1 = A;`
184			`bcd2 = alu_a;`
185			`result = alu_result;`
186			`STATUS[C] = alu_status[C];`
187			`STATUS[V] = alu_status[V];`
188			`STATUS[5] = 1;`
189			`STATUS[B] = alu_status[B];`
190			`STATUS[I] = alu_status[I];`
191			`STATUS[D] = alu_status[D];`
192
193			`case (alu_opcode)`
194			`// BIT - Bit Test`
195			`BIT_ZPG, BIT_ABS: begin`
196			`result = A & alu_a;`
197			`end`
198
199			`// BRK - Force Interrupt`
200			`BRK_IMP: begin`
201			`STATUS[B] = 1'b1;`
202			`end`
203
204			`// CLC - Clear Carry Flag`
205			`CLC_IMP: begin`
206			`STATUS[C] = 1'b0;`
207			`end`
208
209			`// CLD - Clear Decimal Flag`
210			`CLD_IMP: begin`
211			`STATUS[D] = 1'b0;`
212			`end`
213
214			`// CLI - Clear Interrupt Disable`
215			`// TODO: verify if this should be supported by 6507`
216			`CLI_IMP: begin`
217			`STATUS[I] = 1'b0;`
218			`end`
219
220			`// CLV - Clear Overflow Flag`
221			`CLV_IMP: begin`
222			`STATUS[V] = 1'b0;`
223			`end`
224
225			`// NOP - No Operation`
226			`//NOP_IMP: begin`
227			`// Do nothing :-D`
228			`//end`
229
230			`// PLP - Pull Processor Status Register`
231			`PLP_IMP, RTI_IMP: begin`
232			`STATUS = alu_a;`
233			`end`
234
235			`// STA - Store Accumulator`
236			`// PHA - Push A`
237			`// TAX - Transfer Accumulator to X`
238			`// TAY - Transfer Accumulator to Y`
239			`TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin`
240			`result = A;`
241			`end`
242
243			`// STX - Store X Register`
244			`// TXA - Transfer X to Accumulator`
245			`// TXS - Transfer X to Stack pointer`
246			`STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin`
247			`result = X;`
248			`end`
249
250			`// STY - Store Y Register`
251			`// TYA - Transfer Y to Accumulator`
252			`STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin`
253			`result = Y;`
254			`end`
255
256			`// SEC - Set Carry Flag`
257			`SEC_IMP: begin`
258			`STATUS[C] = 1'b1;`
259			`end`
260
261			`// SED - Set Decimal Flag`
262			`SED_IMP: begin`
263			`STATUS[D] = 1'b1;`
264			`end`
265
266			`// SEI - Set Interrupt Disable`
267			`SEI_IMP: begin`
268			`STATUS[I] = 1'b1;`
269			`end`
270
271			`// INC - Increment memory`
272			`INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin`
273			`result = alu_a + 1;`
274			`end`
275
276			`// INX - Increment X Register`
277			`INX_IMP: begin`
278			`result = X + 1;`
279			`end`
280
281			`// INY - Increment Y Register`
282			`INY_IMP : begin`
283			`result = Y + 1;`
284			`end`
285
286			`// DEC - Decrement memory`
287			`DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin`
288			`result = alu_a - 1;`
289			`end`
290
291			`// DEX - Decrement X register`
292			`DEX_IMP: begin`
293			`result = X - 1;`
294			`end`
295
296			`// DEY - Decrement Y Register`
297			`DEY_IMP: begin`
298			`result = Y - 1;`
299			`end`
300
301			`// ADC - Add with carry`
302			`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
303			`if (alu_status[D] == 1) begin`
304			`if (A[3:0] > 9) begin`
305			`bcd1 = A + 6; // A = A - 10 and A = A + 16`
306			`end`
307			`if (bcd1[7:4] > 9) begin`
308			`bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16`
309			`end`
310			`if (alu_a[3:0] > 9) begin`
311			`bcd2 = alu_a + 6;`
312			`end`
313			`if (bcd2[7:4] > 9) begin`
314			`bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16`
315			`end`
316			`end`
317
318			`{STATUS[C],result} = bcd1 + bcd2 + alu_status[C];`
319			`if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))`
320			`STATUS[V] = 1;`
321			`else`
322			`STATUS[V] = 0;`
323
324			`if (alu_status[D] == 1) begin`
325			`if (result[3:0] > 9) begin`
326			`result = result[3:0] + 6; // A = A - 10 and A = A + 16`
327			`end`
328			`if (result[7:4] > 9) begin`
329			`result = result[7:4] + 6; // A = A - 10 and A = A + 16`
330			`STATUS[C] = 1;`
331			`end`
332			`end`
333			`end`
334
335			`// AND - Logical AND`
336			`AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin`
337			`result = A & alu_a;`
338			`end`
339
340			`// CMP - Compare`
341			`CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin`
342			`result = A - alu_a;`
343			`STATUS[C] = (A >= alu_a) ? 1 : 0;`
344			`end`
345
346			`// EOR - Exclusive OR`
347			`EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin`
348			`result = A ^ alu_a ;`
349			`end`
350
351			`// LDA - Load Accumulator`
352			`// LDX - Load X Register`
353			`// LDY - Load Y Register`
354			`// TSX - Transfer Stack Pointer to X`
355			`LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,`
356			`LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,`
357			`LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,`
358			`TSX_IMP : begin`
359			`result = alu_a;`
360			`end`
361
362			`// ORA - Logical OR`
363			`ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin`
364			`result = A \| alu_a;`
365			`end`
366
367			`// SBC - Subtract with Carry`
368			`SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin`
369			`if (alu_status[D] == 1) begin`
370			`if (A[3:0] > 9) begin`
371			`bcd1 = A + 6; // A = A - 10 and A = A + 16`
372			`end`
373			`if (bcd1[7:4] > 9) begin`
374			`bcd1 = bcd1[7:4] + 6; // A = A - 10 and A = A + 16`
375			`end`
376			`if (alu_a[3:0] > 9) begin`
377			`bcd2 = alu_a + 6;`
378			`end`
379			`if (bcd2[7:4] > 9) begin`
380			`bcd2 = bcd2[7:4] + 6; // A = A - 10 and A = A + 16`
381			`end`
382			`end`
383
384			`{STATUS[C],result} = bcd1 - bcd2 - ~alu_status[C];`
385			`if ((bcd1[7] == bcd2[7]) && (bcd1[7] != alu_result[7]))`
386			`STATUS[V] = 1;`
387			`else`
388			`STATUS[V] = 0;`
389			`end`
390
391			`// ASL - Arithmetic Shift Left`
392			`ASL_ACC : begin`
393	145	gabrielosh	`//{STATUS[C],result} = A << 1;`
394			`{STATUS[C],result} = {A,1'b0};`
395	141	creep	`end`
396			`ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin`
397	145	gabrielosh	`//{STATUS[C],result} = alu_a << 1;`
398			`{STATUS[C],result} = {alu_a,1'b0};`
399	141	creep	`end`
400
401			`// LSR - Logical Shift Right`
402			`LSR_ACC: begin`
403	145	gabrielosh	`//{result, STATUS[C]} = A >> 1;`
404			`{result,STATUS[C]} = {1'b0,A};`
405	141	creep	`end`
406			`LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin`
407	145	gabrielosh	`//{result, STATUS[C]} = alu_a >> 1;`
408			`{result,STATUS[C]} = {1'b0,alu_a};`
409	141	creep	`end`
410
411			`// ROL - Rotate Left`
412			`ROL_ACC : begin`
413			`{STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?`
414			`end`
415			`ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin`
416			`{STATUS[C],result} = {alu_a,alu_status[C]};`
417			`end`
418
419			`// ROR - Rotate Right`
420			`ROR_ACC : begin`
421			`{result,STATUS[C]} = {alu_status[C],A};`
422			`end`
423			`ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin`
424			`{result, STATUS[C]} = {alu_status[C], alu_a};`
425			`end`
426
427			`// CPX - Compare X Register`
428			`CPX_IMM, CPX_ZPG, CPX_ABS : begin`
429			`result = X - alu_a;`
430			`STATUS[C] = (X >= alu_a) ? 1 : 0;`
431			`end`
432
433			`// CPY - Compare Y Register`
434			`CPY_IMM, CPY_ZPG, CPY_ABS : begin`
435			`result = Y - alu_a;`
436			`STATUS[C] = (Y >= alu_a) ? 1 : 0;`
437			`end`
438
439			`default: begin // NON-DEFAULT OPCODES FALL HERE`
440	142	gabrielosh	`end`
441	141	creep	`endcase`
442	142	gabrielosh	`STATUS[Z] = (result == 0) ? 1 : 0;`
443			`STATUS[N] = result[7];`
444	141	creep	`end`
445
446			`endmodule`
447